3D Memory Bidirectional Taper Staircase Patterning
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently manufacturing bidirectional taper staircase structures, which are crucial for enhancing memory density and performance, due to limitations in patterning techniques and material replacement processes.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial layers over a substrate, followed by patterning using multiple mask patterns to create contact wells with stepped surfaces, and subsequent replacement of sacrificial layers with electrically conductive layers to form memory stack structures with bidirectional taper staircases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning techniques are used to form bidirectional taper staircase structures, then manufacturing simplicity is maintained, but manufacturing precision and structure complexity are insufficient
Solution Approach 1:
The bidirectional taper staircase structure is segmented into multiple discrete steps along both first and second horizontal directions. Each step is formed by sequential patterning operations using different mask patterns, allowing precise control of each segment's position and dimension. This segmentation enables high manufacturing precision by breaking down the complex three-dimensional structure into manageable two-dimensional patterning stages.
Solution Approach 2:
The invention transitions from conventional two-dimensional planar patterning to three-dimensional bidirectional taper staircase structures by adding vertical dimensionality and a second horizontal direction. Multiple mask patterns with different geometric shapes are employed to define steps in both horizontal directions, creating a true bidirectional taper structure that enhances memory density while maintaining manufacturability through systematic dimensional expansion.
2Reliability
If sacrificial layers are not replaced with electrically conductive layers, then manufacturing process simplicity is maintained, but memory device functionality and performance are insufficient
Solution Approach 1:
Sacrificial layers serve as intermediary structures during the manufacturing process, providing temporary structural support and pattern definition. These sacrificial layers are subsequently replaced with electrically conductive layers that provide the necessary electrical functionality for memory operation. This intermediary approach enables complex structure formation while maintaining process simplicity, as the sacrificial layers can be removed and replaced using standard semiconductor fabrication techniques.
Solution Approach 2:
The invention utilizes parameter changes in material properties during manufacturing. Sacrificial layers with specific removal characteristics are deposited, then electrically conductive layers with different deposition and doping parameters are formed in their place. This parameter transformation approach allows the same physical space to transition from a structural template to a functional electrical component, enhancing device reliability without significantly complicating the manufacturing flow.
3Quantity of substance
If memory density is not enhanced through bidirectional taper staircases, then device complexity is reduced, but memory storage capacity and performance are insufficient
Solution Approach 1:
The bidirectional taper staircase structure implements a nested arrangement where multiple memory stack structures are vertically stacked and laterally offset in a hierarchical pattern. Each staircase step creates a nested configuration that maximizes the number of memory cells per unit area. This nesting approach dramatically increases memory storage capacity by utilizing both vertical and horizontal space efficiently, while the systematic pattern maintains reasonable device complexity through repetitive structural motifs.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.