Bidirectional Trench Memory Cell with Charge Trapping for Multi-Bit Storage
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Solution Overview
Problem
Existing nonvolatile memory cells with charge trapping layers are limited in their ability to store multiple bits effectively, particularly in bi-directional configurations using trenches in substrates.
Innovation Solution
A nonvolatile memory cell design featuring a substrate with two trenches and a channel region connecting them, with charge trapping layers and control gates positioned to enable multi-bit storage through various programming modes, including Fowler-Nordheim tunneling and channel hot electron injection, allowing for the storage of four bits per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional nonvolatile memory cell with a charge trapping layer is used, then the cell can store charges, but it is limited in its ability to store multiple bits effectively
Solution Approach 1:
The memory cell is segmented into two separate trenches instead of using a single trench structure. Each trench contains its own charge trapping layer and control gate, allowing independent charge storage regions that can be programmed and erased separately, thereby enabling multi-bit storage capability
Solution Approach 2:
The invention transitions from a single-trench vertical structure to a dual-trench configuration with a channel region connecting them. This dimensional change creates additional storage regions and enables multiple programming modes (FN tunneling, CHEI) to be applied independently to different trench regions, increasing storage capacity from 1 bit to 4 bits per cell
2Quantity of substance
If bi-directional cells made from trenches in a substrate are used, then the cell structure is simplified, but the ability to store multi-bits is limited
Solution Approach 1:
The dual-trench memory cell structure is designed to support multiple programming and erasing modes including Fowler-Nordheim tunneling and channel hot electron injection. Each trench can be programmed using different modes independently, providing versatility and adaptability for various application requirements while maintaining a relatively simple bi-directional trench structure
3Quantity of substance
If charge trapping layers are added to increase storage capacity, then multi-bit storage becomes possible, but the device complexity increases
Solution Approach 1:
The invention merges two trench structures into a single integrated memory cell unit with a shared substrate and interconnected channel region. By combining the functionality of two separate charge trapping layers and control gates into one coordinated structure, the design achieves 4-bit storage capacity while maintaining manufacturing efficiency and reducing overall device complexity compared to using four independent 1-bit cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient multi-bit storage by utilizing charge trapping layers and control gates to manage charge conduction and programming, enhancing storage capacity and operational flexibility in memory cells.
Implementation Method 1
allowing for the storage of four bits per cell through various programming modes, including Fowler-Nordheim tunneling
Implementation Method 2
channel hot electron injection, allowing for the storage of four bits per cell
Data Source
AI summary
A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.