Bifunctional Chip Routing for Cryogenic Thermal Isolation
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Solution Overview
Problem
Existing micro and nano systems in quantum computing face challenges in thermal management and integration density due to thermal coupling between chips, which limits thermalization and integration density, especially at cryogenic temperatures.
Innovation Solution
An integrated structure with bifunctional routing that combines conductor and superconductor tracks for thermal and electrical functions, allowing for individual heat cages around chips to ensure thermal insulation and high-density integration patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are connected by conductor tracks providing thermal coupling, then electrical connectivity is achieved, but thermal insulation between chips deteriorates
Solution Approach 1:
The routing system is segmented into two distinct types: conductor routing tracks for thermalization and superconductor routing tracks for electrical signaling. This segmentation allows each type of track to perform its specific function independently, preventing thermal coupling through the electrical connection paths while maintaining both thermal and electrical connectivity where needed.
Solution Approach 2:
Different routing tracks are assigned different material properties locally across the integrated structure. Conductor tracks are placed in regions where thermal conduction is desired (for thermalization), while superconductor tracks are placed where electrical signaling is needed without thermal transfer. This local differentiation of material quality resolves the contradiction between electrical connectivity and thermal insulation.
2Reliability
If bumps are used for chip connection, then electrical and thermal connectivity is achieved, but integration density deteriorates
Solution Approach 1:
The thermal conduction function is extracted from the connection interface by using superconductor tracks for electrical connections. Since superconductors exhibit zero electrical resistance and minimal thermal conduction at cryogenic temperatures, the electrical connection can be made without the traditional thermal coupling that comes with bump connections, thereby maintaining high integration density.
Solution Approach 2:
The integrated structure employs composite routing materials - both conventional conductor materials and superconductor materials - within the same structure. This allows the system to leverage the unique properties of superconductors (zero resistance, low thermal conduction) combined with conventional conductors to achieve both reliable chip connection and high integration density.
3Object-affected harmful factors
If thermal insulation between chips is implemented, then thermal management is improved, but thermalization to cryostat deteriorates
Solution Approach 1:
The thermal management system is segmented into localized heat cages formed by conductor tracks around individual chips or chip groups, while superconductor tracks provide thermal isolation between these cages. This segmentation allows each chip to be independently thermalized to the cryostat through its own conductor pathways, preventing cross-thermal coupling while ensuring adequate thermalization.
Solution Approach 2:
Conductor tracks act as intermediary thermal pathways between the chips and the cryostat, while superconductor tracks serve as intermediary barriers that block thermal transfer between chips. This dual-intermediary approach enables selective thermal connectivity: conductor intermediaries facilitate thermalization to the cryostat, while superconductor intermediaries prevent unwanted thermal coupling between chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables effective thermalization and insulation of chips while maintaining high-density integration, optimizing thermal and electrical connectivity for quantum computing applications.
Implementation Method 1
at least one first superconductor routing track made from a superconductor material
Implementation Method 2
the contribution of phonons in thermal conduction attenuating at T3 where T is the temperature considered, thermalisation at these very low temperatures is done mostly by electronic thermal conductivity
Data Source
AI summary
A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.