Bifunctional Routing Structure for Quantum Chip Thermalization

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Solution Overview

Problem

Current integration structures for micro and nano systems in quantum computing fail to provide effective thermalization while maintaining thermal insulation between chips, leading to inefficient heat management at low temperatures.

Innovation Solution

A bifunctional routing structure in three dimensions, combining non-superconducting conductive and superconducting routing tracks and vias, allowing for both thermal insulation and electrical communication between chips, enabling thermalization through conductive components and electrical signal transmission through superconducting components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive routing tracks and vias are used to connect chips, then electrical communication between chips is achieved, but thermal coupling occurs causing heating problems in temperature-sensitive chips

Engineering Contradiction:

Improveelectrical communicationVSAvoidthermal coupling

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The routing system is segmented into two distinct types: superconducting routing tracks/vias for electrical signal transmission and non-superconducting conductive routing tracks/vias for thermal conduction. This segmentation allows electrical and thermal functions to be separated, enabling chips to be electrically connected while thermally isolated.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The integration structure provides a universal routing system that handles both electrical and thermal functions through dedicated pathways. The superconducting tracks serve the universal need for electrical communication while the non-superconducting tracks serve the universal need for thermal management, creating a multi-functional routing infrastructure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Temperature

If superconducting connection bumps are used to connect chips, then thermal insulation between chips is achieved, but chips are insulated from the cryostat preventing proper thermalisation

Engineering Contradiction:

Improvethermal insulation between chipsVSAvoidthermalisation to cryostat

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

Different regions of the integration structure have different thermal properties: the superconducting routing tracks provide thermal insulation in localized areas between chips, while the non-superconducting conductive routing tracks provide thermal conduction pathways to the cryostat. This local differentiation of thermal quality allows simultaneous thermal insulation and thermalisation.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The non-superconducting conductive routing tracks act as intermediary elements that bridge the gap between the thermally insulated superconducting tracks and the cryostat. These intermediary tracks provide the necessary thermal conduction pathway from the chips to the cryostat while the superconducting tracks maintain electrical isolation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables efficient thermal management and insulation between chips, maintaining cryogenic temperatures while allowing for compact and effective electrical communication, enhancing the performance of multi-chip assemblies in quantum computing systems.

Implementation Method 1

at least one superconducting routing track of a superconducting material

Methodology Applied

Scientific EffectSuperconductivity: Superconductivity

Implementation Method 2

thermalisation at these very low temperatures is mainly achieved by electronic thermal conductivity

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20230170305A1Integration structure for connecting a plurality of semiconductor devices, associated methods, assembly and system

Publication Date: 2023.06.01 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

An integration structure for connecting a plurality of semiconductor devices, includes a substrate, a first face and a second face for receiving the semiconductor devices. At the first surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. At the second surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. The integration structure includes at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting conductive track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.