Bifurcated Memory Die Module Offset Stacking
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Solution Overview
Problem
As the number of memory layers in 3D memory structures increases, it becomes challenging to position the logic circuit beneath the 3D memory cell structure, and the heat used to anneal the memory cell structure can adversely affect the logic circuit's operation.
Innovation Solution
The solution involves creating a semiconductor device with a pair of semiconductor dies, where one die includes the memory cell array and the other die includes the logic circuit, fabricated using CMOS technology, which are flip-chip bonded and stacked in an offset configuration, allowing the logic circuit to be separated from the memory cells, thus optimizing the fabrication processes for each and alleviating heat-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the logic circuit is positioned beneath the 3D memory cell structure, then the device complexity is reduced, but the heat from annealing adversely affects the logic circuit operation
Solution Approach 1:
The patent divides the integrated memory into two separate semiconductor dies: a first die containing the memory cell array and a second die containing the logic circuit. This segmentation allows the memory and logic circuit to be fabricated and processed independently, enabling the memory die to undergo high-temperature annealing without exposing the logic circuit to harmful heat effects.
Solution Approach 2:
The logic circuit is extracted from the memory die and placed on a separate die. The second die is then flip-chip bonded to the first die, positioning the logic circuit adjacent to but separate from the memory cell array. This extraction removes the logic circuit from the harmful thermal environment during memory annealing processes.
2Quantity of substance
If the number of memory layers is increased, then the memory capacity is improved, but it becomes harder to position the logic circuit beneath the 3D memory cell structure
Solution Approach 1:
By segmenting the memory and logic circuit onto separate dies, the patent eliminates the constraint of positioning the logic circuit beneath the memory layers. The memory die can be stacked with increased layers without spatial constraints, while the logic circuit resides on a separate die that is flip-chip bonded to the memory die.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. The memory die and logic circuit die are stacked vertically with the logic circuit die flip-chip bonded to the memory die, allowing independent optimization of memory layer count without compromising logic circuit integration.
3Ease of manufacture
If the logic circuit is separated from the memory cells, then the fabrication processes are optimized, but the device complexity increases
Solution Approach 1:
The patent segments the memory cell array and logic circuit onto separate semiconductor dies, allowing each to be fabricated using optimized processes appropriate for its specific requirements. The memory die can undergo specialized high-temperature annealing while the logic circuit die is fabricated using standard CMOS processes.
Solution Approach 2:
After separate fabrication, the two dies are merged through flip-chip bonding, where the second die is bonded to the first die with bonding pads aligned and electrically connected. This merging creates a functionally integrated device while maintaining the manufacturing advantages of separate fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased memory capacity by freeing up space for additional memory cells, optimizes the fabrication processes for memory and logic circuits separately, and maintains a compact footprint without increasing the overall height of the memory module.
Implementation Method 1
a second semiconductor die flip-chip bonded to a surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die
Data Source
AI summary
A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.