Bifurcated Memory Module for 3D Flash Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of memory layers in 3D memory structures for datacenters poses challenges in positioning the logic circuit beneath the memory cell structure, and the heat optimization for memory cell formation can adversely affect the logic circuit's operation, leading to inefficiencies in flash memory device fabrication.
Innovation Solution
The integration of CMOS controller wafers with ASIC logic circuits and memory array logic circuits, using through-silicon vias (TSVs) to electrically and mechanically connect stacked semiconductor dies, forming an integrated flash memory semiconductor device that optimizes both memory management and logic circuit functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory layers in 3D memory structures is increased to meet growing datacenter memory demands, then storage capacity is improved, but it becomes harder to position the logic circuit beneath the 3D memory cell structure
Solution Approach 1:
The patent divides the monolithic integrated device into separate stacked components: memory dies and controller dies. This segmentation allows independent optimization of each component and simplifies the positioning problem by decoupling the logic circuit placement from the memory layer stacking process.
Solution Approach 2:
The patent transitions from a planar positioning approach to a three-dimensional stacked architecture. By moving the logic circuit to a separate die that stacks vertically with the memory dies, the positioning problem is resolved by utilizing the vertical dimension rather than trying to fit everything in a single planar layer.
2Manufacturing precision
If process parameters are optimized for memory array formation with heat treatment, then memory cell structure is improved, but the heat adversely affects the operation of the logic circuit
Solution Approach 1:
By separating the memory array and logic circuit onto different dies, the patent enables independent process optimization. The memory die can undergo high-temperature processing for optimal cell structure formation, while the logic circuit die can be processed at lower temperatures suitable for CMOS operation, eliminating the thermal conflict.
Solution Approach 2:
The patent applies different process conditions to different components: high-temperature processing is applied locally to the memory die for optimal cell formation, while the logic circuit die receives gentler processing conditions. This local quality approach allows each component to be optimized for its specific requirements without compromising the other.
Data Source
AI summary
A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.