Big Integer Arithmetic via Radix Conversion in Processors
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Solution Overview
Problem
Current computer processors lack efficient methods for performing big integer arithmetic operations, particularly 256-bit multiplication, which is crucial for public key cryptography and elliptic curve cryptography, leading to inefficiencies in cryptographic algorithms like ECDSA and RSA.
Innovation Solution
Introducing new instructions and hardware that enable 256-bit multiplication and squaring operations, reusing existing 52x52-bit multipliers and adders in floating-point units to produce 512-bit results, with additional microoperations to handle the calculations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new instructions and hardware are introduced for 256-bit multiplication, then the performance of big integer arithmetic is significantly enhanced, but the device complexity increases
Solution Approach 1:
The patent reuses existing 52x52-bit multipliers and adders in floating-point units to perform 256-bit multiplication operations. By making the existing hardware multi-functional, the patent achieves big integer arithmetic capability without adding dedicated new hardware circuits, thus improving productivity while minimizing the increase in device complexity
Solution Approach 2:
The patent breaks down 256-bit multiplication into multiple smaller operations using existing 52x52-bit multipliers. The large integer multiplication is segmented into several smaller multiplication tasks that can be handled by existing hardware components, enabling big integer arithmetic through composition of smaller operations
2Device complexity
If existing 52x52-bit multipliers are reused for 256-bit multiplication, then hardware resources are minimized, but the number of microoperations required increases
Solution Approach 1:
The patent employs dynamic allocation and orchestration of existing hardware resources to perform 256-bit multiplication. The system dynamically coordinates multiple 52x52-bit multipliers and adders through a sequence of microoperations, adapting the use of existing hardware to achieve larger computational tasks without requiring dedicated static hardware for each operation size
3Device complexity
If 256-bit multiplication is implemented using existing floating-point units, then additional hardware resources are minimized, but the precision requirements for cryptographic algorithms must be strictly maintained
Solution Approach 1:
The patent changes the operational parameters of existing floating-point units to perform integer arithmetic operations. By reconfiguring the floating-point units to handle integer multiplication and using combinations of 52x52-bit multipliers to achieve 256-bit precision, the patent maintains the required cryptographic precision while utilizing existing hardware resources
Data Source
Figure 1A
Figure 1B
Figure 2A~2C
AI summary
An apparatus and method are described for performing big integer arithmetic operations. For example, one embodiment of a processor comprises: a first source register to store a first 256-bit integer operand; a second source register to store a second 256-bit integer operand; and multiplication logic comprising a set of multipliers and adders to perform a multiplication of the first and second 256-bit integer operands to generate a 512-bit result responsive to a 256-bit multiplication instruction, the multiplication logic to convert a radix representation of the first and second 256-bit integer operands from a first radix representation to a second radix representation selected based on a size of the multipliers and adders used to perform the multiplication and generate a result, and then to convert the result back to the first radix representation.