Bi-Layer EUV Resist Patterning for Low-Roughness Semiconductor Features
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Solution Overview
Problem
As semiconductor devices continue to shrink, the process windows for photolithographic processing have become increasingly tight, leading to challenges in reducing feature size and maintaining device yield due to issues like resist scum and residue causing line width roughness and edge roughness.
Innovation Solution
The implementation of a bi-layer resist process involving a chemically-amplified resist (CAR) as the first layer and a metal-containing photoresist as the second layer, along with extreme ultraviolet (EUV) flood exposure, to reduce scum and residue, improve line width roughness, and enhance pattern fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processing is used to pattern semiconductor devices, then device density and integration are achieved, but resist scum and residue cause line width roughness and edge roughness
Solution Approach 1:
The patent divides the photolithographic process into multiple sequential exposure steps (first exposure, second exposure, third exposure) with different exposure doses and wavelengths. This segmentation allows each exposure step to address specific aspects of pattern formation, reducing the accumulation of resist scum and residue that occurs in single-step processing, thereby improving line width roughness while maintaining pattern fidelity.
Solution Approach 2:
The patent employs parameter changes by varying exposure doses (e.g., 5-20 mJ/cm² for first exposure, 1-5 mJ/cm² for second exposure) and wavelengths (e.g., 193 nm, 248 nm, 365 nm) across different exposure steps. These parameter adjustments optimize the chemical modification of photoresist materials at different stages, minimizing resist scum formation and improving line edge roughness while achieving the desired pattern transfer.
2Area of moving object
If feature size is reduced to increase device density, then higher integration is achieved, but process windows for photolithographic processing become tighter
Solution Approach 1:
The patent segments the patterning process into multiple exposure steps with progressively reduced exposure doses. The first exposure (higher dose: 5-20 mJ/cm²) establishes the primary pattern, while subsequent exposures (lower doses: 1-5 mJ/cm²) refine the pattern edges and remove resist scum. This segmentation enables precise control over line width and edge roughness even as feature sizes decrease to 10 nm and below, effectively extending the usable process window.
Solution Approach 2:
The patent applies partial exposure actions where each subsequent exposure step uses a reduced dose compared to the previous step. This partial action approach allows fine-tuning of pattern formation at each stage, enabling precise control over line width and edge quality without requiring a single high-dose exposure that would exceed process window limits for scaled-down features.
3Manufacturing precision
If exposure dose is increased to improve pattern fidelity, then pattern quality improves, but resist scum and residue increase
Solution Approach 1:
The patent divides the exposure process into multiple steps with decreasing doses: first exposure (5-20 mJ/cm²) for primary pattern formation, second exposure (1-5 mJ/cm²) for edge refinement, and third exposure (0.5-2 mJ/cm²) for scum removal. This segmentation distributes the total exposure dose across stages, achieving high pattern fidelity through cumulative exposure while preventing resist scum formation that would result from a single high-dose exposure.
Solution Approach 2:
The patent implements periodic exposure actions with alternating high-dose and low-dose steps. The periodic application of exposure energy allows the photoresist to undergo controlled chemical modifications at each stage, with lower-dose intervals preventing excessive energy accumulation that would generate resist scum and residue, thereby maintaining high pattern fidelity without harmful byproducts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the amount of scum and residue, improves line width roughness and line edge roughness, and allows for reduced exposure doses, thereby enhancing the yield and performance of semiconductor devices.
Implementation Method 1
The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern
Implementation Method 2
A chemically amplified photoresist layer is formed over the target layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern. Portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer are removed.