Bi-Layer Fin Insulation Structure for GAA Gate Etch Protection
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in maintaining the integrity and functionality of insulation features, particularly in gate-all-around (GAA) semiconductor devices, where insulation features are crucial for isolating and supporting gate structures.
Innovation Solution
The formation of insulation features as bi-layer structures, with a bottom layer of silicon oxide encapsulated by silicon nitride, ensures protection during etching processes and maintains insulation integrity by preventing the formation of metal/oxide interfaces, while also utilizing dielectric pillars to divide fins and gate segments, enhancing isolation and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but insulation features become more vulnerable to damage during etching processes
Solution Approach 1:
The patent applies composite materials by forming a bi-layer insulation structure consisting of a first insulating material layer (e.g., silicon oxide) and a second insulating material layer (e.g., silicon nitride) with different etch selectivities. This composite structure provides both protection during etching processes and maintains electrical insulation functionality, resolving the contradiction between high integration density and insulation feature integrity at reduced feature sizes.
Solution Approach 2:
The patent uses an intermediary approach by introducing a multi-layer insulation structure where the first and second insulating material layers act as protective intermediaries during subsequent etching processes. The layers are designed with different etch selectivities to provide differential protection, allowing the insulation features to survive the etching process that forms gate-all-around structures while maintaining their insulating function.
2Ease of manufacture
If insulation features are formed with single-layer structures, then fabrication is simpler, but they cannot provide adequate protection during etching processes
Solution Approach 1:
The patent forms a composite insulation structure with a first insulating material layer and a second insulating material layer, where each layer has different etch selectivity characteristics. This composite structure provides differential protection during etching processes - the first layer may be etched away in specific regions while the second layer remains to protect the insulation feature, or vice versa. This resolves the contradiction by providing etching protection that a single-layer structure cannot achieve.
Solution Approach 2:
The patent applies local quality by creating insulation structures with spatially varying properties through the multi-layer configuration. Different regions of the insulation feature receive different levels of protection depending on which material layer is present and its etch resistance characteristics. This allows the structure to be vulnerable to etching in some areas while protected in others, enabling the formation of gate-all-around structures without damaging the insulation features.
3Object-affected harmful factors
If multi-layer insulation structures are formed with different etch selectivities, then protection during etching is improved, but device complexity increases
Solution Approach 1:
The patent forms a bi-layer insulation structure where the first and second insulating material layers are deposited sequentially and have different etch selectivities. This composite structure provides tailored protection during etching processes - the layers can be designed so that one layer is preferentially etched while the other remains to protect the underlying insulation feature. The complexity is managed by using only two layers with complementary etch selectivity properties rather than more complex multi-layer configurations.
Solution Approach 2:
The patent applies preliminary action by forming the multi-layer insulation structure before the gate-all-around etching process. The layers are deposited and configured in advance with specific etch selectivity characteristics, so that when the etching process occurs, the insulation features are already protected by the appropriate layer configuration. This preliminary preparation resolves the contradiction by ensuring protection is in place before the harmful etching action occurs.
Data Source
AI summary
Semiconductor devices with insulation structures and methods of fabrication are provided. A semiconductor device includes a first fin structure located over a substrate; a first gate segment located over the first fin structure; a second fin structure located over the substrate; a second gate segment located over the second fin structure; and an insulation feature located between the first fin structure and the second fin structure and located between the first gate segment and the second gate segment, wherein the insulation feature extends laterally from a first sidewall nearest the first gate segment to a second sidewall nearest the second gate segment; wherein the insulation feature includes a bottom layer and a top layer located over the bottom layer; and wherein the top layer forms an uppermost surface of the insulation feature.