Bilayer Gate Dielectric Floating Gate ChemFET Array
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Solution Overview
Problem
Large-scale ISFET sensor arrays face challenges in achieving uniform performance and reducing noise interference due to trapped charge and cross-contamination, especially in dense arrays used for multiplex chemical measurements, which affects the accuracy of analyte detection and concentration measurements.
Innovation Solution
The development of a CMOS-fabricated chemFET array with thin dielectric layers and adhesion layers on floating gates, combined with Correlated Double Sampling (CDS) and column buffer techniques to reduce noise and ensure uniform sensor responses, along with microfluidic structures for precise analyte retention and measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ISFET sensor arrays are made large-scale and high-density, then the measurement capability and analyte detection coverage are improved, but noise interference from trapped charge and cross-contamination increases, reducing measurement precision
Solution Approach 1:
The patent divides the gate dielectric into multiple thin layers (e.g., first gate dielectric layer and second gate dielectric layer) instead of using a single thick layer. This segmentation reduces trapped charge accumulation in each layer while maintaining the overall insulation function, thereby reducing noise interference in high-density sensor arrays
Solution Approach 2:
The patent uses composite gate dielectric structures combining different materials (e.g., silicon oxide and silicon nitride layers) with different dielectric properties. This composite approach optimizes both the insulation performance and trapped charge characteristics, enabling high-density arrays to maintain measurement precision despite increased sensor element density
2Manufacturing precision
If thin dielectric layers are used on floating gates, then manufacturing precision and uniform sensor response are improved, but noise interference from trapped charge may increase
Solution Approach 1:
The gate dielectric is segmented into multiple thin layers rather than using a single thin layer. This segmentation maintains the manufacturing advantages of thin layers (uniform deposition, good adhesion) while distributing the trapped charge problem across multiple interfaces, reducing overall noise interference
Solution Approach 2:
The patent introduces intermediate layers (such as adhesion layers or interface layers) between the floating gate and the gate dielectric, or between different dielectric layers. These intermediary layers act as charge traps or barriers that prevent charge accumulation at critical interfaces, reducing noise while maintaining the benefits of thin dielectric structures
3Measurement precision
If Correlated Double Sampling and column buffer techniques are applied, then noise interference is reduced and measurement accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple noise reduction techniques (Correlated Double Sampling, column buffering, and thin-layer gate dielectric design) into an integrated solution. By merging these approaches at both the circuit level and device structure level, the system achieves superior noise reduction while managing complexity through systematic integration rather than separate independent components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-sensitivity, high-density chemFET arrays that provide accurate and stable measurements of analyte concentrations with reduced noise interference, suitable for applications like nucleic acid sequencing and multiplex chemical analysis.
Implementation Method 1
Floating gate chemical field effect transistor array with bilayer gate dielectric
Data Source
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AI summary
The invention is directed to apparatus and chips comprising a large scale chemical field effect transistor arrays that include an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid for analysis. In one aspect such transistor arrays have a pitch of 10 µm or less and each sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region. In one embodiment, the characteristic of said chemical or biological sample is a concentration of a charged species and wherein each of said chemical field effect transistors is an ion-sensitive field effect transistor having a floating gate with a dielectric layer on a surface thereof, the dielectric layer contacting said sample fluid and being capable of accumulating charge in proportion to a concentration of the charged species in said sample fluid. In one embodiment such charged species is a hydrogen ion such that the sensors measure changes in pH of the sample fluid in or adjacent to the sample-retaining region thereof. Apparatus and chips of the invention may be adapted for large scale pH-based DNA sequencing and other bioscience and biomedical applications.