Bi-Layer Gate Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, high parasitic capacitance in semiconductor structures can lead to lower device speed and unsatisfactory performance, despite existing methods being inadequate in fully addressing this issue.
Innovation Solution
A bi-layer dielectric structure is formed using a low-k boron nitride layer with a high density and an oxygen-free silicon nitride layer, deposited in the same process chamber to reduce parasitic capacitance, which is implemented in various semiconductor structures such as gate spacers, inner spacer features, and isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separation distance between active device regions is reduced to meet smaller technology nodes, then functional density increases, but parasitic capacitance increases leading to lower device speed
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant) by using a bi-layer structure with low-k boron nitride (k<3) as the first dielectric layer. This parameter change reduces parasitic capacitance between closely spaced device regions, allowing functional density to increase while maintaining device speed performance.
Solution Approach 2:
The patent employs a composite dielectric structure consisting of two distinct layers: a first dielectric layer of low-k boron nitride and a second dielectric layer of oxygen-free silicon nitride. This composite structure combines the low dielectric constant property of boron nitride with the oxidation resistance of silicon nitride, achieving both low parasitic capacitance and environmental stability.
2Speed
If low-k dielectric material is used to reduce parasitic capacitance, then device speed improves, but the material becomes susceptible to oxidation during fabrication
Solution Approach 1:
The patent introduces a second dielectric layer of oxygen-free silicon nitride as a protective intermediary over the low-k boron nitride layer. This intermediary layer prevents oxygen from reaching and oxidizing the boron nitride during fabrication processes, thereby maintaining both the low dielectric constant and material stability.
Solution Approach 2:
The patent creates an inert environment by using oxygen-free silicon nitride as the second dielectric layer. This layer acts as a barrier that excludes oxygen from the low-k boron nitride layer, effectively creating an oxygen-free environment that prevents oxidation and maintains material reliability during subsequent fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer dielectric structure effectively reduces parasitic capacitance, enhancing the performance of semiconductor devices by maintaining the low dielectric constant and high density of the boron nitride layer while preventing oxidation, thus sustaining potential damages during fabrication.
Implementation Method 1
a low-k dielectric constant and a high density
Implementation Method 2
the second dielectric layer is less easily to be oxidized than the first dielectric layer
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.