Bi-Layer Gate Spacer Structure for Plasma-Resistant FinFET Etching
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Solution Overview
Problem
Challenges arise in the semiconductor industry with the development of FinFET devices due to high aspect ratios and scaling issues, leading to fabrication and design complexities that affect the performance and reliability of semiconductor transistors.
Innovation Solution
The implementation of a bi-layer gate spacer structure comprising a first gate spacer layer with a higher k-value and a second gate spacer layer with a high density and low k-value, formed through an atomic layer deposition process, which enhances etch resistance and capacitance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer gate spacer structure is used, then the fabrication process is simpler, but plasma resistance is insufficient and spacer loss during etching increases
Solution Approach 1:
The patent applies composite materials by forming a bi-layer gate spacer structure comprising a first gate spacer layer (e.g., silicon nitride) and a second gate spacer layer (e.g., silicon oxynitride). Each layer has different material properties optimized for specific functions: the first layer provides etch resistance while the second layer provides plasma resistance. This composite structure resolves the contradiction by achieving superior plasma resistance without requiring a single complex material, thereby maintaining fabrication simplicity while improving reliability.
Solution Approach 2:
The gate spacer is segmented into two distinct layers with different materials and functions. The first gate spacer layer is optimized for etching resistance to prevent spacer loss, while the second gate spacer layer is optimized for plasma resistance to protect during plasma-based fabrication steps. This segmentation allows each layer to be independently optimized for its specific protective function, resolving the contradiction between plasma resistance and structural complexity.
2Reliability
If the gate spacer layer has high density, then etch resistance is improved, but k-value increases reducing capacitance efficiency
Solution Approach 1:
The patent uses composite materials to resolve the contradiction between etch resistance and capacitance efficiency. The first gate spacer layer (e.g., silicon nitride) is formulated with high density and high etch resistance to prevent spacer loss during etching. The second gate spacer layer (e.g., silicon oxynitride) is formulated with lower k-value to maintain capacitance efficiency. This composite approach allows each layer to independently optimize for its primary function without compromising the other, achieving both high etch resistance and good capacitance efficiency.
Solution Approach 2:
Different regions of the gate spacer structure are assigned different material qualities: the first layer near the fin structure has high density for etch protection, while the second layer has optimized dielectric properties for capacitance efficiency. This local quality differentiation resolves the contradiction by allowing each portion of the structure to have the specific properties needed for its location and function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer gate spacer structure improves plasma resistance and reduces spacer loss during etching, resulting in improved transistor performance and reliability.
Implementation Method 1
The dielectric layer is formed by depositing a layer using an atomic layer deposition process
Implementation Method 2
annealing the as deposited layer in H2O to form the dielectric layer
Data Source
AI summary
A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes forming a dielectric layer, which includes forming an as deposited layer using an atomic layer deposition process, which includes flowing a silicon source precursor into a process chamber at a first flow rate, flowing a carbon and nitrogen source precursor into the process chamber at a second flow rate, and flowing an oxygen source precursor into the process chamber at a third flow rate. A ratio of the first flow rate to the second flow rate to the third flow rate ranges between about one to one to eight and one to one to twelve, and the as deposited layer has a carbon concentration substantially greater than a nitrogen concentration. The method further includes annealing the as deposited layer in an environment including H2O to form the dielectric layer.