Bilayer Memory Stacking With Shared Logic for Low-Leakage Density
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Solution Overview
Problem
Conventional 1T-1C memory cells face challenges in advanced technology nodes due to leakage issues with logic transistors, capacitor scaling, and limited density, particularly when using FEOL transistors, which hinder the integration of high-density and low-power embedded memory.
Innovation Solution
Implementing backend memory using TFTs or layer transfer to form access transistors in the BEOL layer, allowing capacitors to be in upper metal layers with thicker interlayer dielectric and larger metal pitch, and utilizing bilayer memory stacking with shared compute logic circuits between bottom and top memory layers to increase density and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FEOL logic transistors are used in 1T-1C memory cells, then compute logic functionality is integrated, but leakage issues and limited density occur in advanced technology nodes
Solution Approach 1:
The patent segments the memory system into two distinct layers: BEOL memory layers using TFT access transistors for high-density storage, and FEOL memory layers using logic transistors for compute functionality. This segmentation allows each layer to optimize for its specific function, with TFTs providing low-leakage high-density storage and logic transistors providing compute capability, thereby resolving the contradiction between integration and leakage.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by implementing multiple BEOL memory layers above the FEOL substrate. This vertical dimensionality change allows high-density memory storage without increasing footprint, enabling TFT-based memory to achieve higher density while maintaining low leakage, and allows compute logic to be shared across multiple memory layers.
2Quantity of substance
If capacitor size is scaled down to increase density, then memory density improves, but data retention requirements become difficult to maintain
Solution Approach 1:
The patent changes the material parameter of the access transistor from conventional logic transistors to TFTs (thin-film transistors). TFTs have fundamentally different electrical characteristics with lower off-state leakage current, which allows capacitors to be scaled down while maintaining data retention. The lower leakage current of TFTs compensates for the reduced capacitor size, enabling high density without sacrificing data retention.
3Quantity of substance
If multiple memory layers are stacked to increase density, then footprint is reduced, but fabrication complexity and integration difficulty increase
Solution Approach 1:
The patent implements shared compute logic circuits that serve multiple BEOL memory layers simultaneously. The FEOL substrate with logic transistors provides compute functionality that is universally accessed by all stacked BEOL memory layers, reducing the need for duplicate logic circuits in each layer and thereby simplifying fabrication and reducing overall device complexity.
Solution Approach 2:
The patent introduces intermediate connection structures (such as through-silicon vias or interlayer connectors) that facilitate communication between the FEOL substrate and multiple BEOL memory layers. These intermediaries simplify the integration process by providing standardized interfaces between layers, reducing fabrication complexity despite the increased number of layers.
4Reliability
If TFTs are used instead of logic transistors, then leakage is reduced and density increases, but integration of compute logic circuits becomes more difficult
Solution Approach 1:
The patent inverts the conventional approach by placing TFT-based memory layers above the FEOL substrate rather than using TFTs throughout. The FEOL substrate retains logic transistors for compute functionality, while TFTs are used only in the BEOL memory layers. This inversion allows compute logic integration in the FEOL layer while achieving low-leakage high-density memory in the BEOL layers.
Data Source
AI summary
Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.