Bilayer Nanosheet DRAM with Common Gate
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Solution Overview
Problem
Conventional DRAMs are slower due to the need for continuous refreshing, which limits their performance compared to SRAMs, and their complex architectures make it cumbersome to implement two separate gate contacts for biasing one side in inversion and the other in accumulation.
Innovation Solution
A one transistor dynamic random access memory (1T DRAM) device using a bilayer nanosheet channel layer composed of silicon and germanium materials, with a common gate structure that biases one side in accumulation and the other in inversion, simplifying the architecture and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional DRAM architecture with separate gate contacts is used to bias one side in inversion and the other in accumulation, then the device can achieve proper channel biasing, but the device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent combines two separate gate contacts into a single common gate structure that simultaneously biases both sides of the bilayer nanosheet channel. The common gate is positioned to electrically interact with both the silicon layer and germanium layer, allowing unified control of accumulation and inversion regions without requiring separate gate contacts, thereby reducing device complexity while maintaining proper channel biasing
Solution Approach 2:
The common gate structure serves multiple functions: it acts as a single gate contact while simultaneously providing bias control for both accumulation and inversion regions of the bilayer channel. This multi-functional gate design eliminates the need for separate dedicated gate contacts for each region, simplifying the overall device architecture
2Reliability
If conventional DRAM continuous refresh operation is implemented, then data retention is maintained, but the memory access speed decreases due to refresh interruptions
Solution Approach 1:
The patent employs a bilayer nanosheet channel composed of silicon and germanium materials with different electronic properties. The silicon layer and germanium layer exhibit complementary characteristics that enable one region to maintain inversion (for fast access) while the other maintains accumulation (for data retention), allowing the device to achieve both reliability and speed without continuous refresh interruptions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bilayer nanosheet and common gate structure enable efficient biasing of the channel layers, enhancing the memory device's performance by allowing one side to be biased in inversion and the other in accumulation using a single gate structure, thereby improving the memory device's speed and simplifying its implementation.
Implementation Method 1
a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer
Data Source
AI summary
A memory device is provided that includes a bilayer nanosheet channel layer including a silicon (Si) layer and a silicon germanium (SiGe) layer; and a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer to provide one of the silicon layer and the silicon germanium layer is biased in accumulation and one of the first layer and the second layer biased in inversion. The memory devices also includes a floating body region on a front face or rear face of the bilayer nanosheet channel layer.