Bilayer RDL Structure for Fewer Bumps and Lower RC Delay
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Solution Overview
Problem
Existing semiconductor device fabrication processes with MIM capacitors are inadequate in minimizing conductive bumps, leading to increased device size and suboptimal performance at high frequencies.
Innovation Solution
A bilayer redistribution layer (RDL) structure is implemented, where the second RDL layer has a lower surface resistance than the first RDL layer, reducing the number of power and ground bumps and enabling better RC delay performance by using a copper material for the second RDL layer and an aluminum-copper alloy for the first RDL layer, with smaller via pitch for the first RDL layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single RDL structure is used, then the device structure is simpler, but the number of conductive bumps increases leading to larger device size
Solution Approach 1:
The redistribution layer is divided into two separate layers (first RDL layer and second RDL layer) with different functions. The first RDL layer handles signal routing with smaller via pitch, while the second RDL layer handles power and ground distribution with larger bumps, allowing each layer to be optimized independently for its specific function
Solution Approach 2:
The problem is solved by adding a vertical dimension - stacking two RDL layers at different heights. This allows the first RDL layer to use fine-pitch vias for signals while the second RDL layer uses larger bumps for power/ground, effectively separating functions that would otherwise compete for the same planar space
2Reliability
If more conductive bumps are used, then power and ground distribution is improved, but device size increases
Solution Approach 1:
Power and ground distribution is segregated into the second RDL layer, which is dedicated exclusively to power and ground signals. This allows the first RDL layer to focus on signal routing without being constrained by power/ground bump requirements, enabling better overall power distribution while maintaining compact device size
Solution Approach 2:
Different regions of the device have different bump size requirements - the second RDL layer uses larger bumps optimized for power and ground current carrying, while the first RDL layer uses smaller vias for signals. This local optimization of bump sizes according to functional requirements improves power distribution efficiency without unnecessarily increasing device size
3Ease of manufacture
If larger via pitch is used, then manufacturing is easier, but RC delay performance deteriorates at high frequencies
Solution Approach 1:
The via pitch requirement is segmented by function: the first RDL layer uses small via pitch (e.g., 5-10 micrometers) optimized for high-frequency signal routing with low RC delay, while the second RDL layer uses larger bump pitch (e.g., 20-50 micrometers) optimized for power and ground distribution. This functional segmentation allows each layer to have manufacturing parameters optimized for its specific purpose
Solution Approach 2:
Different via pitch characteristics are applied locally to different functional layers. The first RDL layer implements fine-pitch vias where small feature sizes are critical for signal integrity, while the second RDL layer implements coarse-pitch bumps where larger features are acceptable and even beneficial for current distribution. This local quality differentiation resolves the contradiction between manufacturing ease and RC delay performance
Data Source
AI summary
A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the via openings to contact exposed second pads.