Bi-Layer SAC Mask for Gate Protection in Self-Aligned Contacts
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Solution Overview
Problem
In the manufacturing of integrated circuits, the formation of source/drain contact plugs faces challenges in protecting the gate stacks and reducing leakage current during the etching process, as existing methods lack effective protection mechanisms for the underlying gate structures.
Innovation Solution
A bi-layer Self-Aligned Contact (SAC) mask structure is introduced, comprising a dielectric liner and a masking layer with high etching selectivity relative to the Inter-Layer Dielectric (ILD), which protects the gate stacks and reduces leakage by selectively etching the ILD to form source/drain contact openings while maintaining high selectivity to the liner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric hard mask is used to protect gate stacks during source/drain contact plug formation, then the gate stacks are protected, but leakage current increases due to lack of effective protection during etching
Solution Approach 1:
The patent divides the protective mask into two separate layers: a dielectric liner layer deposited conformally on the gate stack, and a patterned masking layer formed over the liner. This segmentation allows the liner to provide continuous protection against leakage while the masking layer enables precise etching control for contact opening formation, resolving the contradiction between protection and leakage reduction.
Solution Approach 2:
The dielectric liner acts as an intermediary layer between the gate stack and the etching process. It provides a protective barrier that prevents direct contact between the etchant and the gate stack, thereby reducing leakage current while still allowing the masking layer to define the contact opening pattern. The liner serves as a mediator that enables both protection and controlled etching.
2Manufacturing precision
If a bi-layer SAC mask structure with high etching selectivity is used, then source/drain contact openings are precisely formed, but the device complexity increases
Solution Approach 1:
The bi-layer mask structure segments the protective function into two distinct layers with different roles: the dielectric liner provides conformal coverage and protection, while the masking layer provides pattern definition. This segmentation enables precise contact opening formation through selective etching, with each layer optimized for its specific function, thereby achieving high precision despite increased structural complexity.
Solution Approach 2:
The masking layer is applied selectively over the dielectric liner only in regions where contact openings need to be formed. This local application allows precise control of the etching process at specific locations while maintaining the protective liner elsewhere, achieving high manufacturing precision for contact openings without unnecessarily increasing complexity across the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer SAC mask effectively reduces leakage current and protects the gate stacks by providing high etching selectivity, ensuring precise formation of source/drain contact plugs and maintaining the integrity of the underlying gate structures.
Implementation Method 1
A bi-layer Self-Aligned Contact (SAC) mask structure is introduced, comprising a dielectric liner and a masking layer with high etching selectivity relative to the Inter-Layer Dielectric (ILD), which protects the gate stacks and reduces leakage by selectively etching the ILD to form source/drain contact openings while maintaining high selectivity to the liner.
Implementation Method 2
A bi-layer Self-Aligned Contact (SAC) mask structure is introduced, comprising a dielectric liner and a masking layer
Data Source
AI summary
A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.