Gate Spacer Air Gap Formation Using Bi-Layer Sacrificial Spacers
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in efficiently forming transistors with precise control over the formation of FinFETs, where the existing methods face difficulties in achieving optimal etch selectivity and minimizing damage to epitaxy structures during the formation of air gaps, leading to suboptimal device performance.
Innovation Solution
The method involves using a bi-layered sacrificial spacer film with different etch selectivities and a gradient silicon nitride layer to control the etching process, ensuring selective etching and reducing damage to epitaxy structures by using phosphoric acid, which allows for precise formation of air gaps and minimizes contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form air gaps, then the etching process can be completed, but damage to epitaxy structures occurs and etch selectivity is insufficient
Solution Approach 1:
The patent applies segmentation by using a bi-layered sacrificial spacer film structure with distinct upper and lower layers. The lower layer has high etch selectivity to the epitaxy structure, while the upper layer provides protective cushioning. This segmented structure enables selective etching of the lower layer to form air gaps without damaging the epitaxy structures, resolving the contradiction between achieving etch selectivity and preventing damage.
Solution Approach 2:
The patent implements beforehand cushioning by placing a sacrificial spacer film between the gate structure and the epitaxy structures before the etching process. This sacrificial layer acts as a cushion that protects the epitaxy structures from direct etching damage. The sacrificial film is selectively removed afterward to form the desired air gaps, thus preventing harm while achieving the manufacturing goal.
2Reliability
If air gaps are formed without protective measures, then the formation process is simple, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the bi-layered sacrificial spacer film structure before the etching process. The lower layer is specifically designed with high etch selectivity to enable controlled removal and air gap formation. This preliminary preparation ensures that when etching occurs, the air gaps are formed with precise control, minimizing contact resistance and improving device performance without requiring complex in-process adjustments.
Solution Approach 2:
The patent utilizes parameter changes by varying the etch selectivity between different layers of the sacrificial spacer film. The lower layer is engineered to have significantly higher etch selectivity compared to the upper layer and the epitaxy structures. By changing the material composition and etch response parameters of each layer, the process achieves controlled air gap formation that optimizes electrical contact while maintaining structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with improved etch selectivity and reduced damage to epitaxy structures, enhancing the performance and reliability of semiconductor devices by optimizing the formation of air gaps and source/drain contact resistance.
Implementation Method 1
The upper portion of the dielectric residue has higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue
Data Source
AI summary
A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.


