Bi-Layer Spacer Masking for Precise Semiconductor Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving small cut features and high precision in lithography due to constraints from the lithography process, particularly in forming mandrels for devices like FinFETs, where scaling down increases complexity and reduces etching accuracy.
Innovation Solution
A bi-layer spacer approach is employed, where a first spacer layer with lower crystalline quality is covered by a second spacer layer with better crystalline quality, acting as an etch mask during etching processes to improve etching selectivity and reduce defects at smaller line widths, enhancing process reliability and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single spacer layer is used as etch mask, then the process is simple, but etching selectivity and precision are insufficient at smaller line widths
Solution Approach 1:
The single spacer layer is divided into multiple spacer layers with different crystalline qualities. Each layer serves a specific function: the first spacer layer provides initial etching resistance, while the second spacer layer with better crystalline quality provides enhanced etching selectivity and precision for small line widths. This segmentation resolves the contradiction by improving etching precision through layered structure without excessive complexity.
Solution Approach 2:
The patent uses composite spacer structure combining materials with different crystalline qualities. The first spacer layer and second spacer layer are deposited sequentially to form a composite structure where each material contributes its specific properties. This composite approach improves etching selectivity and precision while maintaining manageable process complexity.
2Productivity
If lithography process is scaled down to achieve smaller features, then production efficiency increases, but etching accuracy and defect reduction become more difficult
Solution Approach 1:
The patent applies preliminary actions by depositing multiple spacer layers with different crystalline qualities before the etching process. The second spacer layer with better crystalline quality is prepared in advance to provide enhanced etching selectivity. This preliminary preparation ensures high etching accuracy is achieved even when lithography is scaled down for higher productivity.
3Reliability
If spacer layer with better crystalline quality is used throughout, then etching selectivity improves, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent applies local quality by using different crystalline qualities in different spacer layers rather than uniformly high quality throughout. The second spacer layer has better crystalline quality where it is most needed for etching selectivity, while the first spacer layer uses standard quality material. This localized approach improves etching selectivity while maintaining ease of manufacture by not requiring high quality materials everywhere.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer spacer method improves etching selectivity and reduces defects at smaller line widths and critical dimensions, thereby enhancing the reliability and performance of semiconductor device manufacturing by providing sufficient etching resistance and precision.
Implementation Method 1
depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer
Implementation Method 2
depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer
Implementation Method 3
performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, wherein the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer
Data Source
AI summary
A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.