Bimodal Branch Predictor Bits in Instruction Cache

Solution Overview

Problem

Conventional branch prediction techniques in processors are limited by high implementation cost and power consumption, leading to reduced performance and increased energy usage due to misprediction errors.

Innovation Solution

The method involves storing bimodal branch predictor bits in branch instructions within an instruction cache, dynamically updating these bits based on prediction accuracy, and using a prediction circuit to determine when to change the predictor bits, thereby reducing the need for a separate branch history table and minimizing power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional branch prediction techniques are used, then branch prediction capability is provided, but implementation cost and power consumption increase

Engineering Contradiction:

Improvebranch prediction accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges the branch prediction function with the instruction cache by storing bimodal branch predictor bits directly in the branch instruction entries of the instruction cache. This integration eliminates the need for a separate branch history table, reducing implementation cost and power consumption while maintaining branch prediction capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The instruction cache is given multiple functions: it serves both as the standard instruction cache for fetching branch instructions and as the branch history storage for bimodal branch prediction. This multi-functionality reduces the need for dedicated branch prediction hardware, thereby lowering power consumption and implementation cost

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If conventional branch prediction techniques are used, then branch prediction capability is provided, but implementation cost increases

Engineering Contradiction:

Improvebranch prediction accuracyVSAvoidimplementation cost

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the branch prediction function with the instruction cache by storing bimodal branch predictor bits directly in the branch instruction entries of the instruction cache. This integration eliminates the need for a separate branch history table, reducing implementation cost and power consumption while maintaining branch prediction capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The instruction cache is given multiple functions: it serves both as the standard instruction cache for fetching branch instructions and as the branch history storage for bimodal branch prediction. This multi-functionality reduces the need for dedicated branch prediction hardware, thereby lowering power consumption and implementation cost

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If branch prediction is employed to avoid pipeline stalling, then processor performance is improved, but power usage increases due to misprediction

Engineering Contradiction:

Improveprocessor performanceVSAvoidpower usage

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent implements feedback by dynamically updating the bimodal branch predictor bits stored in the instruction cache based on actual branch outcome evaluation. This feedback mechanism allows the predictor to adapt to changing branch patterns, improving prediction accuracy and reducing misprediction-related power consumption while maintaining high processor performance

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9122486B2Bimodal branch predictor encoded in a branch instruction

Publication Date: 2015.09.01 QUALCOMM INC

AI summary

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.