Bimodal Clock Generator for Low-Frequency Power Control
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Solution Overview
Problem
Integrated circuit (IC) devices face challenges in power consumption at low frequencies, where edge-triggered ICs consume excessive power, and self-timed ICs sacrifice performance to account for process-voltage-temperature (PVT) variations, leading to suboptimal operation.
Innovation Solution
A bimodal clock generator that receives an input clock signal and provides an output clock signal, with a pulse generator configured to provide a non-toggling clock control signal for high-frequency mode and a toggling clock control signal for low-frequency mode, allowing for efficient power management and performance optimization by adjusting wordline access durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If IC circuits are operated in edge-triggered mode at high frequency, then performance is improved, but power consumption increases excessively at low frequency
Solution Approach 1:
The patent implements dynamic switching between two operational modes (edge-triggered and self-timed) based on the clock frequency. The bimodal clock generator detects the operating frequency and automatically selects the appropriate mode: edge-triggered mode for high-frequency operation to maintain performance, and self-timed mode for low-frequency operation to reduce power consumption. This dynamic adaptation resolves the contradiction by allowing the system to optimize for either speed or power efficiency depending on operating conditions.
Solution Approach 2:
The patent changes the operational parameter (timing mode) based on the clock frequency parameter. By monitoring the clock frequency and switching between edge-triggered and self-timed modes, the system adapts its behavior to minimize power consumption at low frequencies while maintaining high performance at high frequencies. This parameter-based switching strategy directly addresses the power-performance trade-off.
2Use of energy by moving object
If IC circuits are operated in self-timed mode at low frequency, then power consumption is reduced, but performance is sacrificed to account for PVT variations
Solution Approach 1:
The system dynamically selects between edge-triggered and self-timed modes based on clock frequency. At low frequencies, self-timed mode is selected to reduce power consumption, while at high frequencies, edge-triggered mode is selected to maximize performance. This dynamic mode selection allows the system to achieve low power consumption at low frequencies without permanently sacrificing performance, as performance is optimized when needed.
Solution Approach 2:
The operational mode parameter is changed based on the clock frequency parameter. By switching between modes, the system achieves low power consumption at low frequencies while maintaining high performance at high frequencies, effectively resolving the contradiction between power efficiency and productivity.
3Reliability
If self-timed mode is used to provide margin for PVT variations, then reliability is improved, but speed is reduced
Solution Approach 1:
The system dynamically switches between self-timed mode (providing PVT margin) and edge-triggered mode (providing high speed) based on operating conditions. At low frequencies where PVT variations are less critical, self-timed mode provides sufficient margin with lower power consumption. At high frequencies where performance is paramount, edge-triggered mode delivers maximum speed while maintaining reliability through the robustness of the edge-triggered architecture.
Data Source
AI summary
An apparatus relates generally to a clock generator is disclosed. The clock generator is coupled to receive an input clock signal and further coupled to provide an output clock signal. An address and control register is coupled to receive an address signal and the output clock signal. An access generator is coupled to receive the output clock signal. The clock generator includes: an input node coupled to receive the input clock signal; at least one pulse generator coupled to the input node to receive the input clock signal and further coupled to provide a clock control signal; and a control gate coupled to the input node to receive the input signal and further coupled to the at least one pulse generator to receive the clock control signal. The clock control signal is provided in a non-toggling state for a high-frequency mode and in a toggling state for a low-frequency mode.