Bimodal Disable Circuit for Clock Duty Cycle Preservation

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Solution Overview

Problem

Integrated circuits, particularly clock distribution circuits, face uneven degradation of pFETs due to Negative Bias Temperature Instability (NBTI) and other degradation processes, leading to duty cycle distortions in clock signals.

Innovation Solution

A bimodal disable circuit that alternates the logic level of the output signal during disable cycles, using a counter to transition the logic level between logic high and logic low for every other disable cycle, thereby distributing the degradation evenly across nFETs and pFETs in series-connected inverters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the clock distribution circuit input is selectively disabled to conserve power, then power consumption is reduced, but uneven degradation of pFETs occurs due to NBTI

Engineering Contradiction:

Improvepower consumptionVSAvoidpFET degradation uniformity

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies periodic action by alternating the disabled logic level between logic high and logic low in successive disable periods. This periodic switching ensures that different sets of pFETs experience stress alternately, distributing the NBTI degradation evenly across all pFETs in the clock distribution circuit while maintaining power savings during disabled periods.

Inventive Principle:

Principle #19Periodic action

2Manufacturing precision

If the clock distribution circuit input is continuously enabled, then duty cycle accuracy is maintained, but power consumption increases

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidpower consumption

Core Design Contradiction:

Manufacturing precisionVSLoss of energy

Solution Approach 1:

The patent uses periodic action to alternate between enabled and disabled states with switching of logic levels during disabled periods, achieving both power savings and duty cycle accuracy

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that even during disabled periods, the alternating logic levels keep the pFETs evenly degraded, preserving the circuit's ability to maintain accurate duty cycles when re-enabled

Inventive Principle:

Principle #20Continuity of useful action

3Device complexity

If a single logic level is used during disable cycles, then circuit operation is simplified, but duty cycle distortion occurs due to uneven pFET degradation

Engineering Contradiction:

Improvecircuit operation complexityVSAvoidduty cycle accuracy

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies periodic action by switching between logic high and logic low levels during disabled periods, which distributes degradation evenly across pFETs and prevents duty cycle distortion while adding minimal complexity to the control mechanism

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8519767B2Methods, apparatuses, and circuits for bimodal disable circuits

Publication Date: 2013.08.27 MICRON TECHNOLOGY INC

AI summary

Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.