BiMOS Emitter Height Control via Self-Aligned Recess
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Solution Overview
Problem
In BiCMOS architectures, the emitter silicon patterned by a damascene process results in increased emitter resistance due to its upper edge being above the CMOS gate, affecting switching frequency, and is height-dependent on layout specifics, leading to variability of ±30 nm or more.
Innovation Solution
A method involving a substrate with a layer stack comprising isolation layers and a sacrificial layer, where a window is formed to accommodate a collector and base layer, with an emitter layer overfill and selective removal to achieve independent emitter height from the MOS gate, using a combination of deposition and dry-etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the emitter silicon is patterned by a damascene process with the upper edge above the CMOS gate, then the emitter can be self-aligned relative to the collector and base, but the emitter resistance increases due to longer feed line length
Solution Approach 1:
The patent transitions from a planar emitter structure to a three-dimensional structure by forming the emitter within a recess that extends vertically into the substrate. This vertical dimension allows the emitter to be positioned lower relative to the CMOS gate while maintaining self-alignment, thereby reducing the horizontal feed line length and associated resistance without sacrificing alignment precision.
2Manufacturing precision
If the emitter is patterned by a poly-CMP process with a stop on the GC topography, then the emitter can be formed with controlled height, but pattern breaking occurs at the wafer edge and emitter height shows strong dependence on layout specifics with variability of more than ±30 nm
Solution Approach 1:
The patent performs preliminary actions by forming the emitter recess and positioning the emitter structure before finalizing the gate conductor topology. This allows the emitter height and position to be established independently of the specific gate layout, preventing the layout-dependent variability that occurs when emitter patterning is performed after gate formation with CMP processes.
Solution Approach 2:
The patent segments the emitter formation process into distinct stages: forming the recess structure, positioning the emitter material, and then completing the gate conductor. This segmentation allows each step to be optimized independently, ensuring uniform emitter characteristics across different layout configurations without the compounding effects seen in integrated CMP-based processes.
3Manufacturing precision
If a fully self-aligned emitter structure is implemented, then the emitter position is precisely controlled relative to collector and base, but the process complexity increases and costs rise due to additional manufacturing steps
Solution Approach 1:
The patent merges the formation of the emitter recess with the existing isolation layer structure and combines the emitter positioning step with the collector and base formation processes. By integrating these functions into a unified process flow rather than treating them as separate sequential steps, the patent achieves fully self-aligned emitter positioning without proportionally increasing overall process complexity.
Data Source
AI summary
A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.