Bin-Packed Control Word Cache for Parallel Compute Arrays
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Solution Overview
Problem
Current processing architectures are ill-suited for handling large, complex datasets, leading to inefficiencies and increased costs in data processing tasks such as generating invoices, processing payments, and machine learning tasks, due to inflexible designs and overwhelming data volumes.
Innovation Solution
A parallel processing architecture utilizing a two-dimensional array of compute elements with bin packing, where compressed control words are generated, linked, and ordered by a compiler to enable efficient execution of tasks, reducing storage fragmentation and improving throughput through operationally sequenced execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional processing architectures are used to handle large datasets, then data processing tasks can be performed, but processing efficiency and throughput are reduced due to inflexible designs and overwhelming data volumes
Solution Approach 1:
The processing architecture is segmented into multiple independent processing elements arranged in a two-dimensional array, where each element can independently process portions of the dataset. This segmentation allows parallel processing of large datasets, significantly improving throughput while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from traditional one-dimensional or hierarchical processing architectures to a two-dimensional array configuration of processing elements. This dimensional change enables more efficient data flow patterns and parallel processing capabilities, addressing the throughput limitation without proportionally increasing system complexity
2Quantity of substance
If control words are stored in non-compressed format in control word cache, then access and execution are straightforward, but storage space is wasted due to fragmentation
Solution Approach 1:
A decompression mechanism acts as an intermediary between the compressed control word cache and the processing elements. The compressed control words are stored efficiently in the cache, and the decompression intermediary translates them into executable form, thereby maximizing storage capacity while maintaining ease of operation through automated decompression
Solution Approach 2:
The control words are stored in a compressed parameter state in the cache, reducing the space required. The system dynamically changes the parameter state from compressed storage format to decompressed execution format through the decompression mechanism, thereby optimizing both storage capacity and operational simplicity
Data Source
AI summary
Techniques for parallel processing based on a parallel processing architecture with bin packing are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A plurality of compressed control words is generated by the compiler. The plurality of control words enables compute element operation and compute element memory access. The compressed control words are operationally sequenced. The compressed control words are linked by the compiler. Linking information is contained in at least one field of each of the compressed control words. The compressed control words are loaded into a control word cache coupled to the array of compute elements. The compressed control words are loaded into the control word cache in an operationally non-sequenced order. The plurality of compressed control words is ordered into an operationally sequenced execution order, based on the linking information.