Binarized Neural Network Hardware Optimization
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Solution Overview
Problem
Existing artificial neural networks, particularly convolutional neural networks, require a large number of parameters and high memory and power consumption, making them inefficient for resource-constrained environments, and existing studies on binarized neural networks lack practical optimal models and hardware implementations.
Innovation Solution
A method for searching and implementing an optimal binarized neural network (BNN) model and hardware architecture that reduces hardware cost and power consumption while maintaining inference accuracy, using a computer-implemented apparatus to find optimal design parameters for the number of layers and channels, and incorporating components like line buffers, XNOR logic gates, and batch-normalization units in a neural processing unit (NPU) pipeline structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If convolutional neural networks are used to extract features of input data, then feature extraction capability is improved, but memory requirement increases
Solution Approach 1:
The patent applies parameter changes by transitioning from standard floating-point precision to low-precision binary representations. Weights and activations are quantized to 1-bit values (-1 and +1), dramatically reducing memory requirements while preserving sufficient feature extraction capability for many applications.
Solution Approach 2:
The patent employs binary neural networks as a simplified, resource-efficient alternative to full-precision CNNs. By using binary weights and activations, the system creates a lightweight model that consumes minimal memory, suitable for resource-constrained environments where full-precision networks would be prohibitively large.
2Adaptability or versatility
If the number of hidden layers is increased to implement higher artificial intelligence, then intelligence level is improved, but hardware cost increases
Solution Approach 1:
The patent changes the precision parameter of neural network computations from floating-point to binary, enabling deeper networks to be implemented with reduced hardware resources. This parameter transformation allows the system to achieve higher intelligence levels through increased layer depth without proportionally increasing hardware cost.
Solution Approach 2:
The patent segments the neural network into binary-weighted layers with specialized hardware support. By dividing the computation into discrete binary operations that can be efficiently implemented in hardware, the system achieves better scalability and reduced overall hardware requirements compared to conventional floating-point implementations.
3Quantity of substance
If binarized neural network is used to reduce parameter size, then memory efficiency is improved, but inference accuracy may degrade
Solution Approach 1:
The patent systematically explores different precision parameters for weights and activations, identifying optimal binary representations that balance model size reduction with accuracy preservation. By carefully selecting binary quantization schemes and applying them consistently across the network, the system achieves significant compression while maintaining acceptable inference performance.
Solution Approach 2:
The patent introduces dynamic elements to the binary neural network, such as dynamic batch normalization and adaptive thresholding, which help compensate for the loss of precision during binary quantization. These dynamic adjustments allow the network to maintain higher accuracy despite using reduced-precision binary parameters.
Data Source
AI summary
A computer-implemented apparatus installed and executed in a computer to search an optimal design of a neural processing unit (NPU), a hardware accelerator used for driving a computer-implemented artificial neural network (ANN) is disclosed. The NPU comprises a plurality of blocks connected in a form of pipeline, and the number of the plurality blocks and the number of the layers within each block of the plurality blocks are in need of optimization to reduce hardware resources demand and electricity power consumption of the ANN while maintaining the inference accuracy of the ANN at an acceptable level. The computer-implemented apparatus searches for and then outputs an optimal L value and an optimal C value when a first set of candidate values for a number of layers L and a second set of candidate values for a number of channels C per each layer of the ANN is provided.