Binary Neural Network Accelerator With Lazy Bit Line Reset
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Solution Overview
Problem
Existing binary neural network accelerators for charge domain in-memory computation face challenges in improving energy efficiency due to high energy consumption from bit line connections, accuracy losses when operating at sub/near threshold voltage, and the need for constant bit line resets.
Innovation Solution
A high-energy-efficiency binary neural network accelerator is designed with 0.3-0.6V sub/near threshold 10T1C multiplication bit units using series capacitors and a voltage amplification array, incorporating a lazy bit line reset scheme to reduce energy consumption and maintain accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines are connected with a large number of parallel capacitors for charge domain in-memory computation, then computation capability is improved, but energy consumption increases significantly
Solution Approach 1:
The patent divides the bit line into multiple segments, each with its own capacitor, rather than using a single long bit line with one capacitor. This segmentation allows for localized charge storage and reduces the total capacitance load on the bit line, thereby reducing energy consumption while maintaining computation capability. The segmented approach enables independent charging/discharging of individual segments, improving energy efficiency.
Solution Approach 2:
The patent implements periodic reset operations for the bit lines at optimized intervals rather than continuous reset. By determining optimal reset timing based on computation patterns, the system reduces unnecessary reset operations and their associated energy consumption while maintaining computational accuracy. This periodic action approach balances computation capability with energy efficiency.
2Use of energy by moving object
If the binary neural network accelerator operates at sub/near threshold voltage to reduce power consumption, then energy efficiency is improved, but accuracy losses occur
Solution Approach 1:
The patent changes the voltage operating point to sub/near threshold levels (0.3V-0.6V) to reduce power consumption. By carefully selecting and optimizing the threshold voltage parameter, the system achieves low-power operation while maintaining sufficient computational accuracy for binary neural network applications. This parameter change approach enables energy-efficient operation without catastrophic accuracy degradation.
Solution Approach 2:
The patent incorporates error compensation mechanisms that anticipate and correct for accuracy losses before they become critical. By pre-calibrating the system and implementing compensation algorithms, the patent cushions against the inherent accuracy losses from sub/near threshold operation, maintaining acceptable inference accuracy while benefiting from reduced power consumption.
3Reliability
If constant reset of bit lines is implemented after each convolution to maintain accuracy, then computational reliability is improved, but energy consumption increases
Solution Approach 1:
The patent replaces constant reset operations with periodic reset operations performed at optimized intervals. By analyzing computation patterns and determining when resets are actually necessary, the system reduces the frequency of reset operations while maintaining computational reliability. This periodic approach significantly reduces the energy overhead associated with continuous resetting.
Solution Approach 2:
The patent implements selective resetting of only those bit line segments that require it, rather than resetting the entire bit line array after each convolution. By identifying and resetting only the necessary portions, the system maintains computational reliability where needed while reducing unnecessary reset operations and their associated energy consumption in segments that don't require resetting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves peak energy efficiency of 18.5 POPS/W and 6.06 POPS/W, improving energy efficiency by 21× and 135× compared to previous works, while minimizing inference accuracy losses.
Implementation Method 1
capacitors in the 4T1C memory XNOR logical unit are connected in series to an accumulated bit line ABL; a multiplication result directly generates a final convolution result on the accumulated bit line ABL through charge distribution of the capacitors
Implementation Method 2
a voltage amplification array with a size of 20×L, wherein each column is designed with 20 low-voltage amplification units with different transistor sizes
Data Source
AI summary
A high-energy-efficiency binary neural network accelerator applicable to artificial intelligence Internet of Things is provided. 0.3-0.6V sub/near threshold 10T1C multiplication bit units with series capacitors are configured for charge domain binary convolution. An anti-process deviation differential voltage amplification array between bit lines and DACs is configured for robust pre-amplification in 0.3V batch standardized operations. A lazy bit line reset scheme further reduces energy, and inference accuracy losses can be ignored. Therefore, a binary neural network accelerator chip based on in-memory computation achieves peak energy efficiency of 18.5 POPS/W and 6.06 POPS/W, which are respectively improved by 21× and 135× compared with previous macro and system work [9, 11].