Low-Transistor Binary Adders With Voltage Restoration Blocks
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Solution Overview
Problem
Existing binary adders in CMOS technology are limited by high transistor count, semiconductor area, and power dissipation, particularly in advanced technology nodes, and suffer from voltage swing degradation and increased latency in multi-bit operations.
Innovation Solution
Implementing binary adders with a logic block for summation and a restoration block to compensate for voltage level losses, combined with high Fan-in AND gates, reducing transistor count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If CMOS gates are used for binary addition, then power dissipation is reduced compared to single-type MOSFETs, but transistor count and semiconductor area increase
Solution Approach 1:
The adder circuit is segmented into distinct functional blocks: a logic block for performing the addition operation and a restoration block for voltage level compensation. This segmentation allows each block to be optimized independently, with the logic block using fewer transistors and the restoration block using standard CMOS inverters to restore voltage levels without adding excessive complexity.
Solution Approach 2:
A restoration block acting as an intermediary is introduced between the logic block output and the final output. This restoration block uses standard CMOS inverters to compensate for voltage level losses and restore full swing voltages, enabling the logic block to use fewer transistors while maintaining signal integrity through the intermediary restoration stage.
2Adaptability or versatility
If more CMOS stages are cascaded to handle higher functions, then arithmetic operations capability is improved, but semiconductor area and power dissipation increase
Solution Approach 1:
The adder is divided into a compact logic block that performs the core addition function with minimal transistors and a restoration block that handles voltage level restoration. This segmentation reduces the area required for the critical addition function while maintaining the capability for complex arithmetic operations through efficient logic design.
Solution Approach 2:
The invention changes the voltage level parameter by introducing a restoration block that compensates for voltage degradation. This allows the logic block to operate with fewer transistors by restoring full swing voltages at the output, thereby reducing semiconductor area while maintaining arithmetic operation capability.
3Device complexity
If pass-transistor based adders are used to reduce transistor count, then area is reduced, but signal integrity deteriorates due to voltage drop
Solution Approach 1:
A restoration block serves as an intermediary between the pass-transistor based logic block and the output. This restoration block uses standard CMOS inverters to compensate for voltage level losses and restore full swing voltages, thereby maintaining signal integrity while allowing the logic block to use fewer transistors.
Solution Approach 2:
The restoration block changes the voltage level parameter by compensating for voltage drops in the logic block output. By restoring full swing voltages, the system maintains signal integrity (reliability) while the logic block can use a reduced transistor count, resolving the contradiction between device complexity and reliability.
4Reliability
If voltage swing degradation is solved in TG based adders, then signal integrity is improved, but drive power decreases
Solution Approach 1:
The adder is segmented into a logic block that generates sum and carry outputs and a restoration block that restores voltage levels. This segmentation allows the logic block to use transmission gates for full voltage swing and signal integrity while the restoration block efficiently restores levels with controlled power consumption, balancing signal integrity and drive power.
Data Source
AI summary
A method for implementing a logic circuit employing a combination of binary adders of different lengths having summation and carry outputs and AND gates, comprising the steps of replacing at least one known CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing summation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the binary adder circuit, for compensating for voltage level losses when the output is in a high logic state or low logic state. The at least one CMOS AND gate is replaced with a high Fan-in AND gate being above a predetermined threshold, by an improved AND gate consisting of a logic block for performing an AND operation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the AND gate, for compensating for voltage level losses when the output being in a high logic state or low logic state.