Binary Alloy Source-Drain Stressing for Uniform Non-Planar Transistors
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling to smaller features due to variability and imperfections in epitaxial growth, leading to non-uniform conduction and reduced mobility in non-planar transistors, which affect device performance.
Innovation Solution
Incorporating a binary metallic alloy in the source and drain regions of semiconductor devices, which expands or contracts under annealing to induce compressive or tensile stress, enhancing electron or hole mobility and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial growth processes are used in non-planar transistor architectures, then manufacturing simplicity is maintained, but conduction uniformity and carrier mobility deteriorate due to variability and imperfections in the epitaxial layer
Solution Approach 1:
The patent employs a composite source/drain structure consisting of a semiconductor material layer (e.g., silicon or SiGe) combined with a metal layer (e.g., tungsten, cobalt, or nickel). This composite architecture allows the semiconductor portion to provide conformal coverage and stress control while the metal portion ensures low resistance and uniform conduction, thereby resolving the contradiction between conduction uniformity and fabrication complexity
Solution Approach 2:
The invention changes the material parameter composition by introducing metal layers with specific resistivity and stress properties into the source/drain regions. By adjusting the metal layer thickness, composition, and stress characteristics, the patent achieves improved conduction uniformity and carrier mobility while managing the increased fabrication process requirements through controlled parameter variations
2Productivity
If feature size is scaled down to increase device density, then capacity increases, but process variability and fabrication constraints worsen
Solution Approach 1:
The composite semiconductor-metal source/drain structure enables better control over resistance and stress at scaled dimensions. The metal component provides stable electrical properties that are less sensitive to dimensional variations, helping maintain manufacturing precision as features are scaled down to increase device density
Solution Approach 2:
The patent applies different material properties to different regions of the source/drain structure - the semiconductor portion provides stress control and conformal coverage while the metal portion provides low resistance and dimensional stability. This local differentiation of material qualities helps mitigate process variability at scaled dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The binary metallic alloy improves uniformity of current conduction and reduces parasitic resistance, thereby boosting device performance in non-planar transistors like fin-FET and gate-all-around devices.
Implementation Method 1
a binary metallic alloy filling the trench... which expands or contracts under annealing to induce compressive or tensile stress
Implementation Method 2
annealing forms a binary alloy out of the host metal and the seed metal
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a semiconductor channel, a source region adjacent to the semiconductor channel, and a drain region adjacent to the semiconductor channel. In an embodiment, the source region and the drain region each comprise a trench, a conformal silicide lining the trench, and a binary metallic alloy filling the trench.