Binary BCH Decoder Architecture Using Even-Term Syndromes
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Solution Overview
Problem
Existing binary Bose-Chaudhuri-Hocquenghem (BCH) code implementations in hardware, such as ASICs, face challenges in reducing power consumption and size, which are crucial for smaller and more energy-efficient communication systems and NAND flash memories.
Innovation Solution
The proposed solution involves high-speed decoder architectures for binary BCH codes that split data into odd-indexed and even-indexed data, loading only even-indexed syndromes into a variant error-locator array, reducing power consumption and size by eliminating the need for odd-term arrays, and employing systolic units to trade off complexity and latency, with optional modifications to control modules for initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional BCH decoder architectures are used with complete error-locator arrays, then decoding accuracy is maintained, but power consumption and circuit size increase
Solution Approach 1:
The patent extracts and removes the odd-term array from the traditional two-array error-locator structure, retaining only the even-term array. This extraction eliminates the power consumption and circuit complexity associated with the odd-term array while maintaining decoding functionality through modified update equations that operate solely on even-term indices.
Solution Approach 2:
The patent changes the operational parameters of the error-locator array by modifying the update equations to use only even-term syndrome values (S(2i)) and even-term indices. This parameter change allows the system to function with a single array instead of two, reducing power consumption while preserving the essential error-correction capability.
2Reliability
If complete error-locator arrays are implemented, then decoding reliability is maintained, but device size increases
Solution Approach 1:
The patent extracts and removes the odd-term array from the traditional two-array error-locator structure, retaining only the even-term array. This extraction eliminates the circuit area associated with the odd-term array while maintaining decoding functionality through modified update equations that operate solely on even-term indices.
Solution Approach 2:
The patent merges the functionality of both odd-term and even-term processing into a single error-locator array by using modified update equations that handle both cases within one structure. This merging reduces the total circuit area while preserving the complete error-correction capability that would otherwise require two separate arrays.
3Device complexity
If systolic units are used to reduce complexity, then device size decreases, but processing speed may be affected
Solution Approach 1:
The patent segments the decoding process into distinct systolic units that process even-term and odd-term syndromes separately through pipeline stages. This segmentation allows for optimized, simplified hardware implementation of each unit while maintaining overall decoding speed through parallel processing and pipelining across the segmented stages.
Solution Approach 2:
The patent implements dynamic pipelining and parallel processing in the systolic units, where multiple decoding operations can proceed simultaneously through different pipeline stages. This dynamic approach maintains high processing speed despite reduced complexity in individual units, as the system exploits temporal and spatial parallelism.
Data Source
AI summary
Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (Ω)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (Ω)}(0)(x).