Binary Circuit Compilation for SIFA Attack Resistance
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Solution Overview
Problem
Existing countermeasures against differential fault analysis (DFA) and statistical ineffective fault analysis (SIFA) attacks do not adequately prevent the extraction of sensitive information, as they assume that outputs unaffected by faults do not leak information, which is not always the case.
Innovation Solution
A circuit compiling device and method that reduce the number of ineffective faults, particularly single-bit ineffective faults, by representing function output bits as sums of interpolation terms and using XOR subcircuits to ensure that faults introduced in wires always affect at least one function output bit, thereby making SIFA attacks more difficult.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing countermeasures against DFA are applied (redundancy introduction), then protection against differential fault analysis is improved, but the circuit complexity increases and cannot prevent SIFA attacks
Solution Approach 1:
The patent changes the structural parameters of the circuit by representing function output bits as sums of interpolation terms and using XOR subcircuits instead of traditional redundant computation structures. This parameter change achieves both simplified circuit design and effective protection against both DFA and SIFA attacks simultaneously.
Solution Approach 2:
The circuit is segmented into distinct conjunction subcircuits and XOR subcircuits, where each component has a specific function. This segmentation allows for modular design that reduces overall complexity while maintaining security properties against fault analysis attacks.
2Device complexity
If traditional circuit design is used, then circuit simplicity is maintained, but the number of ineffective faults increases making SIFA attacks feasible
Solution Approach 1:
By changing the computational structure to use interpolation terms and XOR operations, the patent transforms the circuit parameters to eliminate ineffective faults while keeping the overall design relatively simple and systematic.
Solution Approach 2:
Interpolation terms serve as intermediary elements between input bits and output bits. These intermediaries ensure that any fault introduced in the circuit propagates to the output, eliminating ineffective faults without requiring complex additional structures.
3Reliability
If redundancy is introduced to detect faults, then DFA protection is improved, but the assumption that unaffected outputs don't leak information is violated
Solution Approach 1:
The interpolation terms act as mediators that connect all circuit elements to the output. This ensures that any fault, whether detected or not, ultimately affects the output in a detectable way, preventing information leakage through supposedly unaffected outputs.
Solution Approach 2:
The circuit structure provides implicit feedback through the XOR subcircuits that combine interpolation terms. This feedback mechanism ensures that any deviation from correct computation, including ineffective faults, manifests in the output, preventing information leakage.
Data Source
AI summary
Some embodiments are directed to a circuit compiling device for compiling a function into a binary circuit and a function evaluation device for evaluating a function using such a binary circuit. The binary circuit comprises conjunction subcircuits each computing a conjunction of function input bits and XOR subcircuits each computing a function output bit. Each function output bit may be represented as a sum of interpolation terms, the plurality of function input bits and the interpolation terms of the one or more function output bits together forming a plurality of interpolation terms. A conjunction subcircuit computes an interpolation term as a conjunction of two interpolation terms. A XOR subcircuit computes a function output bit as a XOR of interpolation terms. Thereby, the first interpolation term and second interpolation term are also used in XOR subcircuits, hence the binary circuit has a smaller number or likelihood of ineffective faults.