Sequential Binary Code Decoding With Parallel LLR Grouping
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Solution Overview
Problem
The complexity of binary IRPA code-based BICM-ID decoders in wireless communication systems hinders efficient data throughput, particularly in non-Gaussian channel environments, where existing decoding methods fail to achieve intended performance.
Innovation Solution
The proposed solution involves an inner decoder with a first grouping unit, LLR symbol selection, conversion, and BCJR processing units, which reduce complexity by grouping bits, calculating and converting LLR values, and performing BCJR algorithms to minimize performance degradation while maintaining high processing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an IRPA code-based BICM-ID decoder is used to achieve throughput close to logical channel capacity in non-Gaussian channels, then data throughput is improved, but decoding complexity becomes very high
Solution Approach 1:
The inner decoder is divided into multiple parallel processing units, each handling a specific subset of bits. The decoder processes bits in groups rather than sequentially, with each processing unit operating independently on its assigned bit subset, enabling parallel computation and reducing overall decoding complexity while maintaining throughput performance
Solution Approach 2:
The patent transforms the decoding process from a sequential single-dimension operation to a multi-dimensional parallel structure. By organizing bit processing across multiple dimensions (different processing units operating simultaneously on different bit groups), the system achieves reduced complexity while preserving the iterative decoding capability necessary for high throughput in non-Gaussian channels
2Productivity
If iterative decoding between inner and outer decoders is performed to achieve high throughput, then channel capacity utilization is improved, but processing time increases
Solution Approach 1:
The system performs preliminary grouping and organization of bits before the iterative decoding process begins. By pre-organizing the bit structure and preparing processing groups in advance, the iterative decoding can proceed more efficiently with reduced processing time per iteration, maintaining high channel capacity utilization while minimizing time loss
Solution Approach 2:
The parallel processing structure ensures that useful decoding actions continue simultaneously across multiple processing units throughout the iterative process. Rather than sequential execution where processing stops between iterations, multiple units operate continuously and concurrently, reducing total processing time while maintaining the iterative refinement necessary for high channel capacity utilization
Data Source
AI summary
The present disclosure relates to a 5G or pre-5G communication system to be provided to support a data transmission rate higher than that of a 4-G communication system, such as LTE, and subsequent communication systems. An apparatus according to one embodiment of the present invention can comprise: a first grouping unit for performing repeated decoding by using an outer decoder and an inner decoder, and grouping, in correspondence to a decoding order, a bit stream, which is received from the outer decoder, from a receiver of a system using binary irregular repeat partial accumulate codes to the inner decoder device; an LLR symbol selection unit for calculating indices of grouped bits having the maximum probability value among the grouped bits, and selecting and outputting a predetermined number of grouped bit LLR values by using the indices of the grouped bits having the maximum probability value; an LLR symbol conversion unit for converting the grouped bit LLR values outputted from the LLR symbol selection unit into symbol LLR values, and outputting the same; a Bahl-Cocke-Jelinek-Raviv (BCJR) processing unit for performing a BCJR algorithm operation on the symbol LLR values; a bit LLR calculation unit for converting an output of the BCJR processing unit into bit LLR values; and a second bit grouping unit for grouping the bit LLR values by predetermined bit units.