Binary Arithmetic Coding with Parallel Re-Normalization for Real-Time CABAC

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Solution Overview

Problem

Existing video coding techniques, such as H.264, face challenges in achieving real-time processing while maintaining high image quality, as they require either lower compressibility or increased quantization step sizes, which compromise image quality.

Innovation Solution

A binary arithmetic coding device that updates coding range widths and probabilities based on symbol ratios, using a binary arithmetic re-normalization unit to generate ternary data strings and convert them into binary data strings efficiently, allowing for real-time processing with high image quality by reducing clock cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If binary arithmetic coding (CABAC) is used to achieve high compressibility and high image quality, then coding efficiency and image quality are improved, but the amount of computation increases making real-time operation difficult

Engineering Contradiction:
Improvecoding efficiencyVSAvoidreal-time processing capability
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent segments the binary arithmetic coding process into multiple independent processing units (first processing unit, second processing unit, third processing unit, fourth processing unit) that operate in parallel. Each unit handles a specific aspect of the coding process (range calculation, probability update, bit generation, normalization), allowing simultaneous execution of multiple coding operations and achieving real-time processing while maintaining high compressibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic probability modeling where probability values are continuously updated based on coding context. The processing units dynamically adjust range widths and probability estimates during the coding process, enabling adaptive compression that maintains high efficiency while the parallel architecture ensures real-time performance

Inventive Principle:
Principle #15Dynamics

2Productivity

If CAVLC is used to enable real-time operation, then processing speed is improved, but compressibility and image quality deteriorate

Engineering Contradiction:
Improvereal-time processing capabilityVSAvoidcompressibility
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By dividing the arithmetic coding process into parallel processing units, the patent achieves the real-time processing speed of simpler methods while implementing the high-compressibility arithmetic coding algorithm. The segmentation allows the system to process multiple data elements simultaneously, reducing overall processing time to meet real-time requirements

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters of the coding system by using parallel processing to reduce the effective processing time per data element. This allows the system to use more computationally intensive arithmetic coding operations while still meeting real-time deadlines, thereby achieving both high compressibility and real-time performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8072359B2Binary arithmetic coding device
Publication Date: 2011.12.06 NTT ELECTORNICS CORP
  • US8072359B2 patent drawing
  • US8072359B2 patent drawing
  • US8072359B2 patent drawing

AI summary

An object of the present invention is to provide a binary arithmetic coding device that allows real-time processing with a higher image quality. At a timing at which a ternary data string for a target bit is outputted, an updated coding range width and an updated range width of less probability are outputted. For that reason, while a binary conversion unit (32) and an f value retention processor (33) convert the ternary data string into a binary data string to output a coded bit, a binary arithmetic re-normalization unit (31) is allowed to perform a processing of binary arithmetic coding for the next bit.