Binary Arithmetic Coding Re-Normalization for Real-Time CABAC

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Solution Overview

Problem

H.264 binary arithmetic coding techniques face challenges in achieving real-time processing while maintaining high image quality due to high computational requirements and frequent stalls in arithmetic encoding, making them unsuitable for real-time operations.

Innovation Solution

A binary arithmetic coding device is designed with a binary arithmetic re-normalization unit, binary conversion unit, and f value retention processor that processes binary data by updating coding range widths and handling ternary data conversion efficiently, allowing for real-time processing with high image quality by separating processing loops and reducing computational cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CABAC (Context-Adaptive Binary Arithmetic Coding) is used to achieve high compressibility and image quality, then coding efficiency and image quality are improved, but processing time increases and real-time operation becomes difficult

Engineering Contradiction:
Improvecoding efficiencyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the binary arithmetic coding process into two independent stages: (1) codeILow update stage and (2) output bit generation stage. This segmentation allows each stage to be processed separately and in parallel, reducing the total processing time while maintaining the high compressibility benefits of CABAC.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs codeILow update in advance (first stage) before generating output bits (second stage). By completing the codeILow update beforehand, the system eliminates waiting time and enables continuous processing, achieving real-time operation without sacrificing coding efficiency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If CAVLC (Context-Adaptive Variable Length Coding) is used to enable real-time processing, then processing speed is improved, but compressibility and image quality deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoidcompressibility
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

By segmenting the CABAC process into two stages, the patent achieves processing speed comparable to CAVLC while maintaining CABAC's superior compressibility. The segmented structure eliminates the bottleneck that previously prevented real-time operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the processing parameters by separating codeILow update from output bit generation, allowing independent optimization of each stage. This enables the system to achieve both high processing speed and high compressibility, resolving the trade-off between CAVLC and traditional CABAC.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If re-normalisation is performed frequently in binary arithmetic coding, then coding accuracy is maintained, but processing stalls occur and real-time operation becomes difficult

Engineering Contradiction:
Improvecoding accuracyVSAvoidprocessing continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments re-normalisation operations into the first stage (codeILow update), separating them from the second stage (output bit generation). This prevents re-normalisation from causing processing stalls in the critical output generation phase, maintaining both coding accuracy and processing continuity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By performing re-normalisation as part of the preliminary codeILow update stage, the system ensures that all necessary accuracy-maintaining operations are completed before output bit generation begins. This eliminates interruptions and enables continuous real-time processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2190122B1Binary arithmetic coder
Publication Date: 2017.01.04 NTT ELECTORNICS CORP
  • EP2190122B1 patent drawing
  • EP2190122B1 patent drawing
  • EP2190122B1 patent drawing

AI summary

An object of the present invention is to provide a binary arithmetic coding device that allows real-time processing with a higher image quality. At a timing at which a ternary data string for a target bit is outputted, an updated coding range width and an updated range width of less probability are outputted. For that reason, while a binary conversion unit (32) and an f value retention processor (33) convert the ternary data string into a binary data string to output a coded bit, a binary arithmetic re-normalization unit (31) is allowed to perform a processing of binary arithmetic coding for the next bit.