In-Memory Binary Complement Crossbar Multiplication With Simpler ADCs
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Solution Overview
Problem
Conventional analog in-memory computing (AIMC) hardware accelerators face inefficiencies in area, power consumption, latency, and computational accuracy due to issues with digital and analog weight storage, digital-to-analog and analog-to-digital conversion errors, and circuit non-idealities.
Innovation Solution
Implement a matrix-vector multiplication device using binary complement inputs, a crossbar array with differential analog conductance, and a digital COMP counter to perform matrix-vector multiplication, eliminating the need for duplicate weights, differential ADCs, and P/N counters, and reducing the complexity of ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional analog in-memory computing hardware accelerators use digital and analog weight storage, then computational functionality is achieved, but area consumption increases and power efficiency deteriorates
Solution Approach 1:
The patent merges digital weight storage and analog weight storage into a unified crossbar array structure where each weight element can be configured to store either digital or analog values. This integration eliminates the need for separate storage mechanisms and reduces overall hardware area while maintaining compatibility with both storage types.
Solution Approach 2:
The crossbar array weight elements are designed with multi-functionality to accommodate both digital and analog weight storage modes. Each weight element can universally store either digital values or analog conductance values, providing flexibility and reducing the need for dedicated storage structures for each type.
2Productivity
If conventional AIMC hardware uses digital-to-analog and analog-to-digital conversion, then computational operations are performed, but conversion errors occur and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the problematic digital-to-analog and analog-to-digital conversion stages from the conventional AIMC architecture. By directly supporting both digital and analog operations within the crossbar array, the system removes the conversion steps that introduce errors and consume power, thereby improving both precision and efficiency.
3Adaptability or versatility
If conventional AIMC hardware uses duplicate weights for differential storage, then weight representation is achieved, but device complexity increases
Solution Approach 1:
The patent merges the representation of duplicate weights into a single unified weight storage structure. Instead of storing separate duplicate weight values, the system uses a single weight element that can represent both digital and analog weight values, thereby reducing structural complexity while maintaining adaptability.
4Productivity
If conventional AIMC hardware uses differential ADCs and P/N counters, then computational results are obtained, but circuit complexity and area increase
Solution Approach 1:
The patent extracts and removes the complex differential ADCs and P/N counters from the conventional architecture. By directly computing results within the crossbar array using simplified conversion mechanisms, the system eliminates the need for these complex external components, thereby reducing overall device complexity and area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, improves computational accuracy, and simplifies ADC design by maintaining a constant maximum current, leading to enhanced circuit area and power efficiency.
Implementation Method 1
each weight is encoded as a differential analog conductance of at least two resistive memory devices
Data Source
AI summary
A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.