Binary Delay Chain With Selector Fault Testing
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Solution Overview
Problem
Existing delay circuits in integrated circuits lack flexibility and testability, making it difficult to detect faults in selector circuitry and requiring larger area and power consumption.
Innovation Solution
Configurable delay chains using binary delay blocks with balanced delay and bypass branches, incorporating test circuitry for fault detection and modular, compact layout, enabling high testability and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed delay circuits are used to address timing violations, then timing requirements are met, but flexibility and testability are reduced
Solution Approach 1:
The delay circuit is divided into multiple binary delay blocks, each contributing a different binary-weighted delay amount. This segmentation allows the total delay to be flexibly adjusted by selecting which blocks are activated, resolving the contradiction between fixed timing compliance and flexible adaptability.
Solution Approach 2:
The delay circuit transitions from a fixed delay implementation to a dynamic, configurable delay structure where individual delay blocks can be selectively enabled or disabled. This dynamic configuration capability allows the circuit to adapt to different timing requirements while maintaining reliable operation.
2Reliability
If conventional delay circuits are used, then delay function is provided, but testability of selector circuitry is difficult
Solution Approach 1:
Test circuitry is integrated into each binary delay block to perform preliminary fault detection on the selector circuitry. This preliminary testing capability allows faults to be detected before they affect overall circuit operation, maintaining reliable delay function while improving testability.
Solution Approach 2:
Dedicated test circuitry acts as an intermediary between the selector circuitry and the observation points. This intermediary test circuitry facilitates fault detection by providing explicit test signals and observation mechanisms that make selector faults detectable without disrupting the normal delay function.
3Reliability
If delay circuits are added to address timing mismatches, then timing violations are corrected, but area and power consumption increase
Solution Approach 1:
The delay circuit is segmented into binary-weighted blocks that can be selectively activated. This segmentation allows the minimum necessary delay to be implemented using only the required blocks, reducing the total area occupied compared to a full fixed delay circuit, while still correcting timing violations effectively.
Solution Approach 2:
The delay circuit utilizes parameter changes in the form of binary-weighted delay blocks where each block contributes a different delay amount. By changing which blocks are active, the total delay can be adjusted to match timing requirements precisely, minimizing the area required while maintaining timing violation correction capability.
Data Source
AI summary
An integrated circuit includes a configurable delay chain, which contains a chain of binary delay blocks. Each binary delay block includes the following. Inputs receive an input signal, a select signal and a test control signal. A delay branch transmits the input signal with a delay, and a bypass branch transmits the input signal without the delay. Selector circuitry is connected to the delay branch and to the bypass branch. The selector circuitry selects either the delay branch or the bypass branch according to the select signal. According to the test control signal, test circuitry produces a test signal to test the selector circuitry.