Binary Differential Demodulator With Nested Multi-Error Correction
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Solution Overview
Problem
Existing non-redundant multi-error correcting binary differential demodulators face limitations in achieving higher order error correcting capabilities due to exponential increases in memory requirements and error propagation vulnerabilities, particularly in syndrome register and pattern detector modules.
Innovation Solution
A novel algorithm for a non-redundant multi-error correcting binary differential demodulator is introduced, featuring a differential detectors module, an error signal generator module, and an error detection and correction module, which simplifies error detection and correction, reduces memory requirements, and eliminates pattern detection processes by using a nested hierarchy of lower-order demodulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher order error correcting capability is implemented in existing NEC binary differential demodulators, then error correction performance is improved, but memory requirements increase exponentially
Solution Approach 1:
The demodulator is divided into multiple functional modules: differential detector module, syndrome generator module, and error correction module. Each module handles specific tasks independently, allowing the system to achieve higher error correction capability without proportionally increasing overall memory requirements. The segmentation enables efficient memory usage by storing only essential syndrome information rather than complete error patterns.
Solution Approach 2:
The patent implements a nested structure where syndrome information from lower-order error correction is integrated into higher-order correction processes. The syndrome generator reuses differential detector outputs across multiple correction levels, creating a nested information hierarchy that reduces redundant storage and achieves higher error correction capability with manageable memory growth.
2Reliability
If higher order error correcting capability is implemented in existing NEC binary differential demodulators, then error correction performance is improved, but device complexity increases
Solution Approach 1:
The demodulator architecture is segmented into distinct functional modules: differential detector module for signal detection, syndrome generator module for error pattern analysis, and error correction module for applying corrections. This modular segmentation manages complexity by localizing functions and enabling independent optimization of each module while achieving high-order error correction capability.
Solution Approach 2:
The syndrome generator module serves multiple functions: it generates syndromes for current error correction, provides feedback for higher-order correction, and reuses differential detector outputs across different correction levels. This multi-functionality reduces the need for separate dedicated circuits for each correction order, thereby managing device complexity while achieving higher error correction capability.
3Measurement precision
If conventional syndrome register and pattern detector modules are used, then error detection is performed, but vulnerability to error propagation increases
Solution Approach 1:
The patent implements feedback mechanisms where corrected outputs from lower-order error correction are fed back into the syndrome generator for higher-order correction processes. This feedback loop allows the system to verify and refine error corrections iteratively, improving detection accuracy while reducing error propagation vulnerability through continuous validation at multiple correction levels.
Data Source
AI summary
An algorithm for a non-redundant multi-error correcting binary differential demodulator simplifies error detection and reduces memory requirements in circuits embodying the same. The demodulator includes a differential detectors (DD) module, an error signal generator (ESG) module, and an error detection-and-correction (EDAC) module. The DD module receives modulated binary input at each of (k+1) differential detectors, each producing (k+1) outputs. The ESG module combines the (k+1)2 output signals with k corrected feedback signals to derive syndromes orthogonal to an erroneous bit to be corrected and generates 2k error signals from the syndromes. The EDAC module generates a correction factor from the 2k error signals and combines the factor with the output of the first order detector delayed by k bits to correct an erroneous bit. The k corrected feedback signals may be derived by successively delaying the corrected erroneous bit. Simplified higher order demodulators may be constructed using a nested hierarchy of lower order demodulators based on the algorithm.