Binary-Encoded Fuse Repair for IC Memory Blocks
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Solution Overview
Problem
Integrated circuit (IC) memories face manufacturing defects due to material or process variations, leading to localized impairment, which existing repair techniques address by using numerous fuses to encode repair information, occupying valuable IC real estate and requiring extensive fuse networks.
Innovation Solution
The method involves using automated test equipment (ATE) to encode fuses with binary-encoded numbers representing defective memory locations, reducing the number of fuses needed by encoding repair information more efficiently, allowing for fewer fuses to represent the same amount of repair data, and utilizing self-test logic and fuse burn logic to implement these encodings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional repair techniques use one fuse per bit of repair information, then complete repair information can be encoded, but the number of fuses required becomes very large (e.g., 20,000 fuses for 20,000 memory blocks)
Solution Approach 1:
Multiple fuses are combined into groups where each group represents a single bit position across all memory blocks. Instead of having separate fuses for each bit in each block, the patent merges them so that a group of fuses collectively encodes one bit position, dramatically reducing the total number of fuses required while maintaining complete repair information capability
Solution Approach 2:
The patent transitions from a one-dimensional arrangement (one fuse per bit per block) to a two-dimensional matrix structure where fuses are organized into groups representing bit positions across multiple blocks. This dimensional reorganization allows the same information to be encoded with fewer physical elements by exploiting the group structure
2Reliability
If numerous fuses are used to encode repair information for distributed memory blocks, then all defective locations can be identified, but valuable IC real estate is occupied
Solution Approach 1:
The patent merges multiple fuse functions into consolidated fuse groups, reducing the total physical footprint of the fuse array on the IC die. By combining fuses that represent the same bit position across different memory blocks into single groups, the overall area required for fuse placement is significantly reduced, freeing up valuable IC real estate for other purposes
3Reliability
If a large number of fuses are implemented, then comprehensive repair coverage is achieved, but the device complexity increases
Solution Approach 1:
The patent merges the complexity of managing individual fuses into a more manageable structure of fuse groups. Instead of dealing with thousands of individual fuse elements, the system operates with a reduced set of groups where each group represents a bit position. This merging reduces the complexity of fuse control logic, addressing, and management while maintaining comprehensive repair coverage across all memory blocks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of fuses required on the IC, conserving space and improving the efficiency of the repair process, allowing the IC to operate normally with fewer fuses, thus optimizing the use of IC real estate.
Implementation Method 1
A common type of fuse comprises a metal region that can be reconfigured from a very low impedance to a very high impedance by briefly subjecting it to a relatively high voltage, thereby 'blowing' or 'burning' the fuse
Data Source
AI summary
Memory blocks in an integrated circuit (IC) chip can be repaired by employing automated test equipment external to the IC chip to aid in burning fuses on the IC chip by encoding the fuses with binary-encoded numbers. Each binary-encoded number represents a bit position of each “1” bit of a repair control word corresponding to a defective memory location. During a repair sequence preceding operation of the IC chip, the binary-encoded numbers are read out of the fuses and used to form a serial stream of repair chain information.


