Binary-to-Gray Conversion Circuit for Glitch-Free Gray Counters
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Solution Overview
Problem
Conventional binary-to-Gray converting circuits using XOR gates suffer from glitches during bit transitions, making timing control difficult and increasing power consumption, while schemes to remove glitches often compromise on setup and hold time margins.
Innovation Solution
A binary-to-Gray converting circuit implemented with a buffer unit and a conversion unit using flip-flops without XOR gates, where the buffer unit generates a data code based on power supply voltage and binary bit signals except the least significant bit, and the conversion unit generates Gray code by latching data bits in response to binary bits, effectively producing glitch-free Gray codes without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If XOR gates are used in binary-to-Gray converting circuits, then the conversion function is achieved, but glitches occur during bit transitions causing timing control difficulty and increased power consumption
Solution Approach 1:
The patent removes XOR gates from the binary-to-Gray converting circuit, extracting the problematic component that causes glitches. The conversion function is achieved without XOR gates by using a different architectural approach with flip-flops and direct logic, eliminating the source of timing issues and power consumption problems while maintaining the essential conversion capability
Solution Approach 2:
The patent replaces the XOR gate-based combinatorial logic system with a sequential logic system using flip-flops. This substitution changes the fundamental mechanism from combinatorial to sequential logic, eliminating glitches by using clocked edges for synchronization and reducing power consumption by avoiding continuous switching in combinatorial paths
2Reliability
If additional circuits are added to remove glitches from binary-to-Gray conversion, then glitch-free operation is achieved, but setup and hold time margins are compromised
Solution Approach 1:
The patent uses the rising edge of the clock signal to preemptively capture the binary bit value before any potential glitch can affect the output. By latching the data at the precise moment of the clock edge, the circuit prepares the correct Gray code bit in advance, ensuring glitch-free operation without adding timing constraints that would reduce setup and hold time margins
Data Source
AI summary
A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.