Binary Input Circuit With Selective Fault Tolerance
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Solution Overview
Problem
The existing triplication method for fault-tolerant electronic circuits requires excessive hardware and energy, and cannot adapt reliability levels based on varying input value requirements, leading to inefficiencies in resource utilization.
Innovation Solution
A fault-tolerant electronic circuit arrangement that differentiates between subsets of input values, providing full fault tolerance for critical inputs and reduced or no fault tolerance for non-critical inputs, using multiple combinational circuit components and a majority voter system to optimize hardware usage and adapt reliability accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system triplication with majority voter is used for fault tolerance, then reliability is improved, but hardware expenditure and energy consumption increase significantly
Solution Approach 1:
The patent applies local quality by differentiating fault tolerance requirements across different input value subsets. Critical inputs (subset X1) receive full fault tolerance protection through triplication, while non-critical inputs (subset X2) use reduced or no fault tolerance. This selective approach maintains reliability where needed while reducing hardware expenditure overall.
Solution Approach 2:
The patent implements dynamics by making the fault tolerance level adaptive based on the input value being processed. The control circuit dynamically selects which subset (X1 or X2) the current input belongs to and activates the appropriate fault tolerance mechanism accordingly. This dynamic adaptation allows the system to vary reliability levels rather than maintaining constant triplication for all inputs.
2Reliability
If system triplication with majority voter is used for fault tolerance, then reliability is improved, but energy consumption increases more than three times
Solution Approach 1:
The patent reduces energy consumption by applying full fault tolerance processing only locally to critical inputs (subset X1) rather than globally to all inputs. For non-critical inputs (subset X2), the system uses reduced fault tolerance or direct processing, significantly lowering the energy burden while maintaining acceptable reliability levels.
Solution Approach 2:
The dynamic selection mechanism allows the system to switch between high-energy full fault tolerance mode (for X1) and low-energy reduced fault tolerance mode (for X2). This dynamic energy management ensures that high energy consumption is incurred only when necessary for critical operations, rather than continuously for all operations.
3Reliability
If system triplication is used uniformly for all inputs, then fault tolerance is achieved, but the system cannot adapt reliability levels for different input requirements
Solution Approach 1:
The patent resolves this contradiction by applying different reliability levels to different input subsets. Critical inputs (X1) receive uniform triplication-based fault tolerance, while non-critical inputs (X2) receive reduced or no fault tolerance. This local differentiation enables the system to adapt reliability levels to match the actual requirements of different input types.
Solution Approach 2:
The control circuit dynamically determines whether the current input belongs to subset X1 or X2 and activates the corresponding fault tolerance mechanism. This dynamic adaptation allows the system to vary reliability levels in real-time based on input characteristics, achieving both fault tolerance where needed and adaptability across different operating conditions.
Data Source
AI summary
Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.