Binary Logic Circuit Division by Modulo Bit Slices
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Solution Overview
Problem
Conventional binary logic circuits for calculating the ratio x/d, where d is a positive integer of the form 2n±1, face inefficiencies in terms of circuit area consumption and latency, with existing methods either requiring significant silicon area or introducing considerable latency through sequential operations.
Innovation Solution
A binary logic circuit configured to form the ratio x/d using a rounding scheme, where each bit slice is generated through a modulo operation and carry bit combination, optimizing the circuit to minimize both area and latency by parallelizing modulo operations and using a combination logic tree with AND and OR gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If long division is used to calculate the ratio, then silicon area consumption is reduced, but latency increases due to sequential operations
Solution Approach 1:
The input variable x is divided into multiple bit selections (segments), and the division operation is performed by calculating bit slices sequentially. Each bit slice is determined by evaluating a modulo operation on a specific bit selection of x, breaking down the complex division into smaller, manageable segments that can be processed efficiently
Solution Approach 2:
The circuit performs periodic modulo operations on different bit selections of the input variable to generate successive bit slices of the quotient. This periodic evaluation pattern allows the circuit to maintain low latency by systematically processing each bit slice in a regular, predictable sequence
2Loss of time
If multiplication by reciprocal is used to calculate the ratio, then latency is reduced, but silicon area consumption increases
Solution Approach 1:
The quotient is segmented into multiple bit slices, where each bit slice corresponds to a specific position in the quotient. This segmentation allows the circuit to generate each bit slice independently through modulo operations, avoiding the need for a full parallel multiplier while maintaining efficient latency performance
Solution Approach 2:
The circuit changes the computational approach from direct multiplication by reciprocal to periodic modulo operations on bit selections. This parameter change in the calculation method enables the circuit to achieve low latency through efficient modular arithmetic rather than requiring large parallel multiplication hardware
3Ease of manufacture
If standard logic units are used for ratio calculation, then ease of manufacture is improved, but both area consumption and latency are suboptimal
Solution Approach 1:
The standard logic unit is enhanced by segmenting the division operation into periodic modulo evaluations on bit selections. This maintains the ease of manufacture using standard logic components while optimizing the internal structure to reduce both area consumption and latency through systematic bit slice generation
Data Source
AI summary
A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.