Binary Logic Circuit for Constant Fraction Integer Multiplication
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Solution Overview
Problem
Existing integrated circuit designs for division operations, especially when the divisor is a constant, are inefficient due to complex logic implementations, consuming more area and resources compared to multiplication operations.
Innovation Solution
A binary logic circuit is designed to perform division as a multiply-add operation by optimizing the values of a, b, and k, where a and b are fixed integers, and k is the smallest integer that satisfies specific modular conditions, allowing the division operation to be expressed as ax+b2k, with the logic circuit optimized to minimize hardware complexity and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If division operation is implemented using conventional logic circuits, then the division function is achieved, but the hardware area and complexity are excessive
Solution Approach 1:
The patent transforms the division operation parameters by expressing 1/q as a binary fraction and using the identity x/q = x*(2^k/q)*2^-k. This parameter transformation converts division into multiplication by a pre-computed constant (2^k/q), followed by a simple right shift, dramatically reducing hardware complexity while maintaining accuracy.
Solution Approach 2:
The patent replaces the mechanical division circuit with a multiplication circuit. By pre-computing the constant a = 2^k/q and storing it in a lookup table or register, the division operation x/q becomes a multiplication x*a followed by a right shift by k bits. This substitution leverages the fact that multiplication is more efficiently implemented in hardware than division.
2Area of stationary object
If division is expressed as multiplication by constant fraction, then area is reduced, but finding optimal a, b, k values is complex
Solution Approach 1:
The patent performs preliminary computation of the constant a = 2^k/q during the design phase. By pre-calculating this value and storing it in a lookup table or register, the complex optimization problem is solved once at design time, allowing simple multiplication and shift operations at runtime. This preliminary action eliminates the need for complex real-time optimization logic.
Solution Approach 2:
The patent uses an approximate value of 1/q by finding the smallest k such that 2^k/q has a manageable binary representation. This partial action approach accepts a small approximation error in exchange for dramatically reduced hardware complexity, using only multiplication and shift operations instead of full division logic.
3Device complexity
If suboptimal expressions of division logic are used, then implementation is simpler, but hardware area consumption increases
Solution Approach 1:
The patent creates a copy of the constant value a = 2^k/q and stores it in a lookup table or register. This pre-computed copy allows the division operation to be performed efficiently using multiplication by this stored constant, avoiding the need for complex division logic while minimizing hardware area. The copied constant value is reused across multiple operations.
Data Source
AI summary
A binary logic circuit is provided for determining a rounded value ofpxq,where p and q are coprime constant integers with p<q and q≠2i, i is any integer, and x is an integer variable between 0 and integer M where M≥2q, the binary logic circuit implementing in hardware the optimal solution of the multiply-add operationax+b2kwhere a, b and k are fixed integers.