Binary Logic Circuit for Constant Modulo Arithmetic
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Solution Overview
Problem
Existing binary logic circuits for calculating y=x mod (2m−1) often consume significant circuit area and introduce delay into the critical path, making them inefficient for digital logic operations.
Innovation Solution
A binary logic circuit comprising reduction logic to reduce x into a sum of two m-bit integers β and γ, and addition logic to calculate the m least significant bits of the sum right-shifted by m, along with exception logic to handle specific input cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional binary logic circuits are used for calculating x mod (2^m-1), then the calculation can be performed, but the circuit area consumed is significant and delay is introduced into the critical path
Solution Approach 1:
The patent segments the n-bit input x into multiple m-bit segments (high-order segment and low-order segment). This segmentation allows the modulo operation to be decomposed into simpler operations on smaller bits, reducing the overall circuit area while maintaining calculation speed. The high-order and low-order segments are processed separately and then combined, avoiding the need for a single large complex circuit.
2Area of stationary object
If conventional binary logic circuits are used for calculating x mod (2^m-1), then the calculation can be performed, but delay is introduced into the critical path
Solution Approach 1:
The patent performs preliminary segmentation of the input x into m-bit segments before the actual modulo calculation. By pre-organizing the input data into manageable segments (high-order and low-order parts), the subsequent calculation steps can proceed in parallel or with reduced dependency chains, thereby minimizing critical path delay without requiring excessive circuit area.
3Ease of manufacture
If standard logic units are used to generate circuit designs from RTL, then circuit design can be automated, but the generated circuits rarely represent the most efficient logic in terms of circuit area or delay
Solution Approach 1:
The patent changes the fundamental parameters of the modulo operation by exploiting the specific properties of modulus (2^m-1). Instead of using generic modulo logic, it transforms the operation into segment-based arithmetic where the input is divided into m-bit segments. This parameter change enables more efficient hardware implementation with reduced area and delay, while still being describable in RTL for automated design tools.
Data Source
AI summary
A binary logic circuit for determining y=x mod (2m−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.