Binary Multiplier Partial-Product Layout for Lower Area and Power
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Solution Overview
Problem
Existing binary multipliers in General Purpose Processors (GPP), Digital Signal Processors (DSP), and hardware accelerators face challenges with high area and power consumption due to the large number of bit combinations and required half- and full-adders, particularly in applications like wireless and wireline communication systems and machine learning algorithms.
Innovation Solution
A novel binary multiplier design that generates and aligns partial products based on selector bits, reduces the number of bits to be added through optimized partial product groupings and uses a Wallace tree combination, thereby minimizing silicon area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional binary multiplier designs are used, then multiplication functionality is achieved, but silicon area and power consumption increase due to large number of bit combinations and adders
Solution Approach 1:
The patent segments the multiplication process into generating two distinct sets of partial products: a first set defining a_i*(b_{i-1}:b_0) + b_i*(a_{i-1}:a_0) and a second set defining a_i*b_i. This segmentation allows for optimized grouping and reduction of bits to be added, thereby reducing silicon area while maintaining multiplication functionality.
Solution Approach 2:
The patent introduces a new dimensional approach by organizing partial products into two separate sets with different structural characteristics. The first set handles cross-term products while the second set handles direct product terms, creating a multi-dimensional organization that enables more efficient reduction trees and reduces the overall adder count.
2Reliability
If traditional binary multiplier designs are used, then multiplication functionality is achieved, but power consumption increases due to large number of bit combinations and adders
Solution Approach 1:
By segmenting partial products into two sets with distinct generation methods, the patent reduces the total number of bits requiring addition operations. Since power consumption in multipliers is directly proportional to the number of active adders and bit combinations, this segmentation directly reduces power consumption while preserving multiplication functionality.
Solution Approach 2:
The patent changes the structural parameters of partial product organization by defining two different sets with different mathematical formulations. This parameter change in how partial products are structured and grouped leads to fewer reduction steps and fewer adders, thereby reducing power consumption.
3Area of stationary object
If optimized partial product generation is used, then silicon area is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the generation of multiple partial products into two consolidated sets that can be processed through unified reduction trees. By combining similar operational patterns into standardized generation units and using systematic shifting and summing procedures, the circuit complexity is managed efficiently while achieving area reduction through optimized resource sharing.
Data Source
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AI summary
An apparatus, method and computer program is described comprising: generating a first set of partial products that define ai∗(bi-1:bo) + bi∗(ai-1:ao) for all values of i, dependent on the values of selector bits ai and bi; generating a second set of partial products that define aibi for all values of i; and shifting and summing the first and second sets of partial products.