Binary Neural Network Noise Simulation for CIM Accuracy

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Solution Overview

Problem

Convolutional neural networks (CNNs) face accuracy degradation when run on binary compute-in-memory (CIM) devices due to noise from process, voltage, and temperature variations, as well as quantization noise introduced by analog-to-digital converters, which are exacerbated by the difference in execution environments between digital and CIM devices.

Innovation Solution

The method involves simulating noise effects during the training of neural networks to account for CIM-specific noise sources, using probabilistic binary neural networks and low-level circuit simulations to generate a noise model that is integrated into a CIM chip simulator, allowing for the generation of robust neural network models suited for operations on CIM arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If neural networks are trained without simulating CIM-specific noise, then training speed and simplicity are improved, but accuracy degradation occurs when deployed on binary CIM devices

Engineering Contradiction:

Improveaccuracy of CNN on binary CIM deviceVSAvoidcomplexity of training simulation system

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by simulating CIM-specific noise effects during the training phase. A noise model is constructed that replicates process, voltage, and temperature variations as well as quantization noise from ADCs. This preliminary simulation prepares the neural network for the actual CIM execution environment, ensuring accuracy without requiring complex post-deployment adjustments.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary noise simulation layer between the standard training process and CIM deployment. This intermediary component generates and injects realistic noise patterns that mimic actual CIM hardware behavior, serving as a bridge that allows networks trained on standard hardware to perform accurately on binary CIM devices.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If conventional von-Neumann computing architectures are used, then processing flexibility is maintained, but data transfer bottlenecks increase due to separated memory and processor modules

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidenergy for data transfer

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent merges memory and processing functions into a unified compute-in-memory architecture. Binary weights are stored directly in memory cells that can perform analog multiplication with input signals, eliminating the need for separate data transfer between memory and processor. This integration dramatically reduces energy consumption and eliminates data transfer bottlenecks while maintaining computational capability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11790241B2Systems and methods for modifying neural networks for binary processing applications

Publication Date: 2023.10.17 QUALCOMM INC

AI summary

In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.