Binary Neural Network Circuits Using XNOR Counting on Programmable ICs
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Solution Overview
Problem
Existing implementations of neural networks on programmable integrated circuits (ICs) are constrained to software and lack efficient hardware solutions for binary representations, limiting their ability to process large machine learning problems effectively.
Innovation Solution
A hardware implementation of binary neural networks on programmable ICs, utilizing a layer of hardware neurons with logic circuits for XNOR operations, counter circuits for bit counting, and compare circuits for threshold comparison, which reduces power consumption and increases processing speed compared to floating-point implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If binary neural networks are implemented in hardware on programmable ICs, then processing speed and power efficiency are improved, but device complexity increases due to the need for specialized logic circuits, counter circuits, and compare circuits
Solution Approach 1:
The hardware neuron is segmented into three distinct functional blocks: logic circuit (for XNOR operations), counter circuit (for bit counting), and compare circuit (for threshold comparison). This segmentation allows each block to be optimized independently while maintaining overall system efficiency, resolving the contradiction by making complexity manageable through modular design.
Solution Approach 2:
The patent replaces traditional floating-point arithmetic operations with binary XNOR operations followed by bit counting. This substitution of computational mechanics dramatically improves power efficiency and speed while reducing the complexity requirements compared to full floating-point hardware implementations.
2Use of energy by moving object
If binary representations are used for weights and activations, then power consumption is reduced and processing speed increases, but implementation is constrained to software rather than hardware
Solution Approach 1:
The patent substitutes software-based binary neural network operations with dedicated hardware circuits that perform XNOR operations, bit counting, and threshold comparison. This hardware implementation maintains the low power consumption benefits of binary representations while eliminating software constraints, enabling high-speed processing in programmable ICs.
3Ease of manufacture
If floating-point or fixed-point multiply-accumulate operations are used in systolic array architecture, then implementation on programmable ICs is established, but power consumption increases and processing speed decreases compared to binary operations
Solution Approach 1:
The patent changes the numerical representation parameter from floating-point or fixed-point to binary representations for weights and activations. This parameter change fundamentally alters the computational operations required, enabling the use of simple XNOR logic circuits instead of complex multiply-accumulate units, thereby reducing power consumption while maintaining implementation feasibility on programmable ICs.
Data Source
AI summary
In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.