Binary Partition Pattern Derivation Using Shift-Based Thresholding
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Solution Overview
Problem
Current 3D-HEVC depth partitioning pattern derivation methods require high memory access rates and increase hardware implementation complexity due to averaging and division operations, which are inefficient and costly in terms of computational resources.
Innovation Solution
The proposed techniques simplify the derivation of binary partition patterns by eliminating the division operation through alternative threshold determination methods, such as using arithmetic right shift operations and pre-defined values, to reduce hardware complexity without compromising coding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If averaging and division operations are used in binary partition pattern derivation, then coding precision is improved, but device complexity and memory access requirements increase
Solution Approach 1:
The patent changes the computational parameters from division operations to multiplication and bit shift operations. Specifically, it uses the formula threshold = (sum of reference samples + offset) >> shift_amount, where the shift amount is derived from block size. This parameter transformation maintains the thresholding function while eliminating the need for complex division hardware.
Solution Approach 2:
The patent substitutes the mechanical division operation with a bit shift operation. Instead of using a division unit that requires complex hardware logic and multiple memory accesses, it uses a simple bit shift unit that can be implemented with basic logic gates, significantly reducing hardware complexity and memory access requirements.
2Productivity
If averaging operations are used in binary partition pattern derivation, then coding efficiency is improved, but memory access rate requirements increase
Solution Approach 1:
The patent performs preliminary accumulation of reference samples during the normal decoding process, storing the sum in a register before threshold calculation. This preliminary action eliminates the need for additional memory accesses during the threshold computation phase, as the sum is already available in fast memory (register/file).
Solution Approach 2:
By replacing the averaging operation (which requires memory access to retrieve individual samples for summation) with a pre-computed sum and bit shift operation, the patent eliminates repeated memory accesses while maintaining the thresholding function, thus improving memory access speed and overall coding efficiency.
3Measurement precision
If division operations are used in binary partition pattern derivation, then coding precision is improved, but processing speed decreases
Solution Approach 1:
The patent transforms the division operation into a bit shift operation by changing the mathematical parameter representation. The threshold is calculated as (sum + offset) >> shift_amount, where the shift amount corresponds to log2(divisor). This parameter transformation maintains numerical precision while enabling faster execution through simple bit manipulation.
Solution Approach 2:
The patent substitutes the slow division operation with a fast bit shift operation. Division requires complex hardware logic and multiple clock cycles, while bit shift can be executed in a single clock cycle using simple logic gates. This substitution dramatically improves processing speed while maintaining the functional equivalence of the threshold calculation.
Data Source
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AI summary
There is disclosed a method, device and computer-readable storage medium for decoding video data. The method includes: obtaining a reference sample array of a video block; obtaining a sum of the reference sample array; calculating a threshold by performing arithmetic right shift to the sum, a shift value of the arithmetic right shift being determined according to size information of the video block; and determining the binary partition pattern by comparing the reference sample array with the threshold.