Binary Phase Detector PLL for Reference-Free Clock Recovery
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Solution Overview
Problem
Existing phase-lock loop (PLL) systems face challenges in synthesizing a clock signal from a data stream, especially at high bit rates, as they often require a dedicated reference signal and may not effectively handle phase locking in digital input data streams without proportional control paths.
Innovation Solution
A PLL circuit and method that utilize a binary phase detector to generate polarity signals indicating the phase relationship between the data stream and feedback signal, which are then filtered and integrated to control a voltage-controlled oscillator, eliminating the need for a dedicated reference signal and enabling phase locking through polarity control paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated reference signal is used in traditional PLL systems, then frequency tracking accuracy is improved, but device complexity and signal requirements increase
Solution Approach 1:
The system uses the data stream itself as the reference signal for phase detection, eliminating the need for external dedicated reference signals. The binary phase detector compares the data stream directly with the feedback signal from the oscillator, allowing the system to self-generate the necessary reference without additional external components or signals.
Solution Approach 2:
The data stream serves multiple functions simultaneously: it is both the input signal to be recovered and the reference signal for phase detection. This multi-functionality eliminates the need for separate reference signal paths and reduces overall system complexity while maintaining frequency tracking capability.
2Reliability
If proportional control paths are used in PLL systems, then phase locking performance is improved, but device complexity increases
Solution Approach 1:
The invention extracts and utilizes only the polarity information from phase comparison, eliminating the need for complex proportional control paths. By focusing on binary polarity detection rather than continuous phase error measurement, the system achieves phase locking with simplified control logic and reduced device complexity.
Solution Approach 2:
The system changes the control parameter from continuous phase error magnitude to binary polarity state. This parameter transformation simplifies the control path by converting analog phase error signals into digital polarity signals, enabling phase locking through simpler digital logic rather than complex analog proportional control.
3Measurement precision
If multiple filter paths with different pulse widths are used, then frequency tracking accuracy is improved, but device complexity increases
Solution Approach 1:
The filtering function is segmented into multiple parallel paths, each with different pulse width characteristics. This segmentation allows the system to process different aspects of the polarity signals simultaneously, improving frequency tracking accuracy through multi-path filtering while keeping each individual path relatively simple.
Solution Approach 2:
The system adds the dimension of pulse width variation across multiple filter paths. By filtering signals through paths with different pulse widths, the system creates a multi-dimensional filtering approach that enhances frequency tracking accuracy by capturing different temporal characteristics of the phase polarity signals.
Data Source
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AI summary
A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.