Binary-Search SRAM CNN Architecture for Noise Reduction
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Solution Overview
Problem
Conventional SRAM-based convolutional neural networks (CNNs) face issues with high complexity, large area requirements, and noise-related inaccuracies due to mismatch and thermal noise, particularly in current-based and charge-sharing-based implementations.
Innovation Solution
The implementation of a binary-search-based SRAM-CNN that compares analog signals and converts them to digital bits, reducing complexity and noise impact by using smaller transistors and capacitors, and employing a binary search mechanism to enhance signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional current-based or charge-sharing-based SRAM implementations are used, then the CNN can perform convolutional operations, but the complexity increases and area requirements become large
Solution Approach 1:
The patent segments the weight representation into two parts: a coarse weight stored in SRAM and a fine weight stored in PCM. This segmentation allows the SRAM to handle only the coarse computation while the PCM provides fine-grained adjustments, reducing the complexity requirements for the SRAM circuitry while maintaining computational efficiency.
Solution Approach 2:
The patent uses a hybrid memory architecture combining SRAM and PCM technologies. The SRAM stores coarse weights and the PCM stores fine weights, creating a composite memory system that leverages the advantages of both technologies: SRAM's speed and PCM's density and low power consumption, thereby reducing overall system complexity.
2Measurement precision
If larger transistors and capacitors are used in conventional SRAM-CNN, then the signal-to-noise ratio improves, but the area increases
Solution Approach 1:
The patent changes the operating parameters by using pulse-width modulation (PWM) to represent weights as duty cycles rather than using large capacitors for charge storage. This parameter change allows for accurate weight representation with smaller transistors and capacitors, maintaining signal-to-noise ratio while reducing area.
Solution Approach 2:
The patent replaces the traditional charge-sharing mechanism (which requires large capacitors) with a PWM-based temporal encoding scheme. Instead of using spatial charge storage, the system uses temporal pulse width modulation to encode weights, substituting a mechanical/electrical charge-based system with a time-based control mechanism that requires smaller components.
3Device complexity
If thermal noise and transistor mismatches are present in conventional SRAM-CNN, then the hardware is simpler, but noise-related inaccuracies increase
Solution Approach 1:
The patent implements feedback mechanisms where the output of the SRAM-CNN is fed back to adjust the PWM duty cycle values. This feedback loop allows the system to compensate for thermal noise and transistor mismatches by continuously refining the weight representations, thereby improving computational accuracy while maintaining hardware simplicity.
Solution Approach 2:
The patent performs preliminary calibration of the PWM duty cycle values during training, pre-compensating for expected thermal noise and transistor mismatches. By preparing the system in advance with calibrated values, the actual runtime operation requires minimal correction, maintaining both simplicity and accuracy.
Data Source
AI summary
One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.