Binary Search Tree Longest Prefix Match Using Embedded Prefix Markers
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Solution Overview
Problem
High-speed routers face bottlenecks in routing throughput due to the complexity and cost of implementing Longest Prefix Match (LPM) in large routing tables, with existing solutions like TCAMs being power-intensive and inflexible, and hash-based structures requiring significant storage and overhead.
Innovation Solution
A packet processing apparatus and method using a binary search tree with embedded prefixes in hash tables, where markers are converted to embedded prefixes to reduce memory consumption and improve routing efficiency, allowing for a more flexible and scalable solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TCAM is used to perform LPM in one memory access, then routing speed is improved, but cost and power consumption increase significantly
Solution Approach 1:
The patent segments the routing table into multiple levels (root level and child levels), with the root level containing a reduced set of entries and child levels containing the remaining entries. This segmentation allows the system to avoid using expensive TCAM for the entire routing table while maintaining fast lookup performance through a two-stage search process.
Solution Approach 2:
The patent extracts a subset of routing table entries to form a root level that can be stored in faster, smaller memory structures. By taking out only the most critical entries for the root level and placing them in SRAM or other fast memory, the system achieves high-speed access without the cost and power consumption of using TCAM for all entries.
2Device complexity
If SRAM is used to store routing table entries, then cost and power consumption are reduced, but routing speed decreases due to multiple memory accesses
Solution Approach 1:
The patent performs preliminary organization of routing table entries into a hierarchical structure with a root level and child levels before the actual lookup operation. The root level is pre-populated with selected entries that enable fast initial filtering. This preliminary arrangement allows subsequent lookups to proceed quickly by first checking the small root level in SRAM, then only accessing child level entries if necessary.
3Device complexity
If hash-based structures with markers are used for LPM, then implementation complexity is reduced, but storage requirements increase due to marker overhead
Solution Approach 1:
The patent extracts and removes the marker overhead that plagues traditional hash-based LPM implementations. By organizing the routing table into a hierarchical structure with explicit level separation, the system eliminates the need for markers to indicate level transitions. This extraction of markers reduces the storage overhead while maintaining implementation simplicity.
4Speed
If the entire routing table is stored on chip, then routing speed is improved, but chip area and cost increase
Solution Approach 1:
The patent segments the routing table into a root level stored on-chip in fast SRAM memory and child levels that can be stored off-chip in slower but larger capacity memory. This segmentation allows the critical path (root level lookup) to be performed quickly on-chip while storing the bulk of the routing table off-chip, thereby achieving fast routing performance without requiring excessive on-chip area.
Data Source
AI summary
In one embodiment, a packet processing apparatus includes interfaces, a memory to store a representation of a routing table as a binary search tree of address prefixes, and store a marker with an embedded prefix including k marker bits providing a marker for an address prefix of a node corresponding to a prefix length greater than k, and n additional bits, such that the k marker bits concatenated with the n additional bits provide another address prefix, packet processing circuitry configured upon receiving a data packet having a destination address, to traverse the binary search tree to find a longest prefix match, compare a key with the k marker bits, extract an additional n bits from the destination address, and compare the extracted n bits with the n additional bits, and process the data packet in accordance with a forwarding action indicated by the longest prefix match.