Binary Process Signal Prediction for Delay-Free Automation Control

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Solution Overview

Problem

In industrial automation control systems, binary process signals from sensors often experience delays due to signal processing and transmission, leading to outdated values that compromise control and regulation quality, particularly in large-scale systems, and existing solutions like clock synchrony are complex and costly.

Innovation Solution

An input module buffers signal curves and employs a neural network to predict binary process signals by learning from edge changes, using a learning phase to establish input patterns and an operating phase to evaluate current values, allowing for timely and accurate forecasting without requiring a dynamic system model or knowledge of physical conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If signal processing and transmission are performed in conventional automation control systems, then the binary process signal is processed and transmitted through the control system, but delays occur leading to outdated values that compromise control and regulation quality

Engineering Contradiction:
Improvecontrol and regulation qualityVSAvoidsignal delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by training a neural network model in advance during a learning phase to predict binary process signal values. The model learns from historical signal curves and is prepared beforehand to provide predictions during operation, eliminating the need to wait for actual signal processing and transmission delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a virtual copy of the binary process signal through neural network prediction. Instead of relying on the actual delayed physical signal transmission, the system generates a predicted signal copy that reflects what the signal value will be, providing current information without the physical transmission delay.

Inventive Principle:
Principle #26Copying

2Loss of time

If clock synchronization is implemented to manage delays, then signal timing is coordinated, but the system complexity increases and costs rise

Engineering Contradiction:
Improvesignal timing controlVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/clock-based synchronization system with a neural network-based prediction system. Instead of coordinating timing across multiple components through clock synchronization, the system uses an intelligent model to predict signal values, substituting complex timing coordination with a simpler prediction mechanism.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If processing cycles are shortened to compensate for outdated values, then control quality improves, but the processing unit experiences increased strain

Engineering Contradiction:
Improvecontrol qualityVSAvoidprocessing unit strain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The neural network prediction creates a virtual copy of the signal processing function, transferring the computational burden from the central processing unit to the prediction model. This allows the processing unit to operate at normal cycle rates while still obtaining current signal values through prediction, reducing strain while maintaining control quality.

Inventive Principle:
Principle #26Copying

Data Source

PatentEP4057087B1A method for providing a predicted binary process signal
Publication Date: 2024.03.06 SIEMENS AG
  • EP4057087B1 patent drawingFigure 1
  • EP4057087B1 patent drawingFigure 2
  • EP4057087B1 patent drawingFigure 3

AI summary

To compensate for a signal delay for a binary process signal (S1), it is proposed to temporarily store further process signals (S2, S3, S4) from further sensors (2, 3, 4) for a predetermined time interval (TB), and – in a learning phase (20) – to a neural network (NN) at a switching time (ts), namely the time at which the binary process signal (S1) exhibits a first edge transition (F1) from logic zero to logic one or a second edge transition (F2) from logic one to logic zero, as a learning time (ts-Tx), which results from the switching time (ts) minus a prediction time interval (Tx). To supply a stimulating input signal pattern (M1,...,M5).