Binary Stream Switching Divider for Fine Fractional Frequency Synthesis
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Solution Overview
Problem
Fractional frequency synthesis from a fixed reference clock using Phase Locked Loops (PLL) results in higher processing overhead due to the need for complex modules and logic, limiting the generation of finer discrete frequencies required for power and performance optimization in dynamic voltage and frequency scaling applications.
Innovation Solution
A binary stream switching controlled modulus divider is employed, utilizing a synchronous binary number counter and cascaded binary stream switching circuits to generate fractional division control signals, reducing processing overhead by simplifying the control logic and generating finer discrete frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fractional division modules (delta-sigma modulator, multi-phase VCO, multi-phase frequency divider) are used to generate finer discrete frequencies, then frequency resolution is improved, but processing overhead and device complexity increase
Solution Approach 1:
The patent combines the counter and binary stream switching circuits into an integrated modulus divider controller structure. The counter unit and binary stream switching units work together as a unified control mechanism, eliminating the need for separate delta-sigma modulator, multi-phase VCO, and multi-phase frequency divider modules. This merging reduces device complexity while maintaining frequency resolution through the binary stream switching mechanism that generates precise division control signals.
2Measurement precision
If complex control logic and multiple modules are employed to achieve fractional frequency synthesis, then finer discrete frequencies are generated, but power consumption and processing overhead increase
Solution Approach 1:
The binary stream switching controlled modulus divider is self-controlling through its internal counter and switching circuitry. The counter automatically generates count values that drive the binary stream switching units, which in turn generate the division control signals without requiring external complex control logic. This self-service mechanism reduces power consumption by eliminating the need for separate control modules and complex logic circuits while maintaining precise frequency granularity.
Data Source
AI summary
A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.